chiark / gitweb /
digispark-with-cable: wip
authorIan Jackson <ijackson@chiark.greenend.org.uk>
Mon, 16 Oct 2023 23:09:40 +0000 (00:09 +0100)
committerIan Jackson <ijackson@chiark.greenend.org.uk>
Thu, 26 Oct 2023 17:10:37 +0000 (18:10 +0100)
Signed-off-by: Ian Jackson <ijackson@chiark.greenend.org.uk>
digispark-with-cable.scad

index 5497431d70780a5dce820d8e64ac5bbd2c792192..69a19e25e3f629eed4c87cc0e22e0bbd9a4cc50f 100644 (file)
@@ -12,10 +12,19 @@ usb_ceil_th = 0.125;
 
 side_wall_th = 1.5;
 
-board_l = 13.56 + 0.2;
+board_l = 17.56 + 0.2;
 board_w = 19.14 + 0.2;
 board_th = 1.92 + 0.1;
 
+sw_to_edge = board_w/2 + 0.1;
+
+small_walls = [
+              [ [0, 0], [-sw_to_edge, -1.0] ],
+              [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
+              [ [3.0, -11.72] ,[sw_to_edge, -13.38] ],
+              [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
+              ];
+
 module BothSides(){
   for (m=[0,1]) {
     mirror([m,0]) {
@@ -30,6 +39,9 @@ module TopSmallWallsPlan() {
                 [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
     }
   }
+  for (w=small_walls) {
+    rectfromto(w[0], w[1]);
+  }
 }
 module TopCeilPlan() {
   BothSides(){