chiark / gitweb /
digispark-with-cable: wip
authorIan Jackson <ijackson@chiark.greenend.org.uk>
Mon, 16 Oct 2023 22:58:26 +0000 (23:58 +0100)
committerIan Jackson <ijackson@chiark.greenend.org.uk>
Thu, 26 Oct 2023 17:10:37 +0000 (18:10 +0100)
Signed-off-by: Ian Jackson <ijackson@chiark.greenend.org.uk>
digispark-with-cable.scad

index 279df344ce3d0dc7fec089b8e648fa8c5c34c068..5497431d70780a5dce820d8e64ac5bbd2c792192 100644 (file)
@@ -14,19 +14,20 @@ side_wall_th = 1.5;
 
 board_l = 13.56 + 0.2;
 board_w = 19.14 + 0.2;
+board_th = 1.92 + 0.1;
 
-module TopSmallWallsPlan() {
+module BothSides(){
   for (m=[0,1]) {
     mirror([m,0]) {
-      rectfromto([ -usb_w/2,              -0.01        ],
-                [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
+      children();
     }
   }
 }
-module BothSides(){
+module TopSmallWallsPlan() {
   for (m=[0,1]) {
     mirror([m,0]) {
-      children();
+      rectfromto([ -usb_w/2,              -0.01        ],
+                [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
     }
   }
 }
@@ -39,7 +40,10 @@ module TopCeilPlan() {
   }
 }
 module TopMainWallsPlan() {
-  
+  BothSides(){
+    rectfromto([ -board_w/2 - side_wall_th, 0            ],
+              [ -board_w/2,                -board_l     ]);
+  }
 }
 
 module Top(){
@@ -47,6 +51,8 @@ module Top(){
     TopSmallWallsPlan();
   linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
     TopCeilPlan();
+  linextr(-board_th, usb_wall_h)
+    TopMainWallsPlan();
 }
 
 Top();