digispark-with-cable: wip progress

Signed-off-by: Ian Jackson <ijackson@chiark.greenend.org.uk>

diff --git a/digispark-with-cable.scad b/digispark-with-cable.scad
index c042d6c1725da693522d6bc1b3d1466ea36ef1f5..069c04bf1ae8ca2820a40a53e8f52eddece2e2cc 100644 (file)
--- a/digispark-with-cable.scad
+++ b/digispark-with-cable.scad
@@ -22,7 +22,8 @@ sw_to_edge = board_w/2 + 0.1;
 front_wall_th = 0.75;
 // egress_w = 8.0;
 
-wall_y_min = -board_l - side_wall_th;;
+wall_y_min = -board_l - side_wall_th; // XXXX remove
+main_y_min = -board_l - side_wall_th;
 ceil_y_min = wall_y_min - 5;;
 
 small_walls = [
@@ -34,6 +35,17 @@ small_walls = [
 chip_cutout = [[ -sw_to_edge + 4.20,    -3.75 ],
               [ -sw_to_edge + 11.95,  -11.90 ]];
 
+strain_w = 2.0 + 0.5;
+strain_t = 1.0 + 0.5;
+strain_pitch_across = 5;
+strain_pitch_along = 10;
+
+// calculated
+
+strain_0_y_c = main_y_min - strain_w/2;
+strain_1_y_c = strain_0_y_c - strain_pitch_along;
+total_y_min = strain_1_y_c - strain_w/2 - side_wall_th;
+
 module BothSides(){
   for (m=[0,1]) {
     mirror([m,0]) {
@@ -77,7 +89,7 @@ module TopMainWallsPlan() {
   }
   FrontWallsPlan(usb_tongue_w_slop);
   rectfromto([ -board_w/2 - side_wall_th + 0, -      board_l   ],
-            [ +board_w/2 + side_wall_th,            wall_y_min ]);
+            [ +board_w/2 + side_wall_th,            total_y_min ]);
 }
 
 module Top(){ ////toplevel
@@ -88,3 +100,6 @@ module Top(){ ////toplevel
   linextr(-board_th, usb_wall_h)
     TopMainWallsPlan();
 }
+
+module Bottom(){ ////toplevel
+}