digispark-with-cable.scad

   1 // -*- C -*-
   2
   3 include <utils.scad>
   4
   5 //tongue_w = 11.92 + 0.4;
   6
   7 usb_w = 12.01 + 0.19;
   8 usb_wall_w = 0.51;
   9 usb_tongue_d = 8.97 - 0.2;
  10 usb_tongue_w_slop = +0.5;
  11 usb_wall_h = 4.54 - 2.04;
  12 usb_ceil_th = 0.425;
  13
  14 side_wall_th = 1.5;
  15
  16 board_l = 17.56 + 0.2;
  17 board_w = 19.14 + 0.2;
  18 board_th = 1.92 + 0.1;
  19
  20 sw_to_edge = board_w/2 + 0.1;
  21
  22 front_wall_th = 0.75;
  23 // egress_w = 8.0;
  24
  25 wall_y_min = -board_l - side_wall_th; // XXXX remove
  26 main_y_min = -board_l - side_wall_th;
  27 ceil_y_min = wall_y_min - 5;;
  28
  29 small_walls = [
  30                [ [0, 0], [-sw_to_edge, -1.0] ],
  31                [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
  32 //             [ [3.0, -11.72],              [sw_to_edge, -13.38] ],
  33                [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
  34                ];
  35 chip_cutout = [[ -sw_to_edge + 4.20,    -3.75 ],
  36                [ -sw_to_edge + 11.95,  -11.90 ]];
  37
  38 strain_w = 2.0 + 0.5;
  39 strain_t = 1.0 + 0.5;
  40 strain_pitch_across = 5;
  41 strain_pitch_along = 10;
  42
  43 // calculated
  44
  45 strain_0_y_c = main_y_min - strain_w/2;
  46 strain_1_y_c = strain_0_y_c - strain_pitch_along;
  47 total_y_min = strain_1_y_c - strain_w/2 - side_wall_th;
  48
  49 module BothSides(){
  50   for (m=[0,1]) {
  51     mirror([m,0]) {
  52       children();
  53     }
  54   }
  55 }
  56 module FrontWallsPlan(slop) {
  57   BothSides(){
  58     rectfromto([ -board_w/2 - side_wall_th,    0             ],
  59                [ -usb_w/2 - slop,              front_wall_th ]);
  60   }
  61 }
  62 module TopSmallWallsPlan() {
  63   for (m=[0,1]) {
  64     mirror([m,0]) {
  65       rectfromto([ -usb_w/2,              -0.01        ],
  66                  [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
  67     }
  68   }
  69   FrontWallsPlan(0);
  70   for (w=small_walls) {
  71     rectfromto(w[0], w[1]);
  72   }
  73 }
  74 module TopCeilPlan() {
  75   difference(){
  76     BothSides(){
  77       rectfromto([ -usb_w/2,              -0.01        ],
  78                  [ 0.1,                   usb_tongue_d ]);
  79       rectfromto([ -board_w/2 - side_wall_th, 0            ],
  80                  [ 0.1,                       ceil_y_min   ]);
  81     }
  82     rectfromto(chip_cutout[0], chip_cutout[1]);
  83   }
  84 }
  85 module TopMainWallsPlan() {
  86   BothSides(){
  87     rectfromto([ -board_w/2 - side_wall_th, 0          ],
  88                [ -board_w/2,                wall_y_min ]);
  89   }
  90   FrontWallsPlan(usb_tongue_w_slop);
  91   rectfromto([ -board_w/2 - side_wall_th + 0, -      board_l   ],
  92              [ +board_w/2 + side_wall_th,            total_y_min ]);
  93 }
  94
  95 module Top(){ ////toplevel
  96   linextr(0, usb_wall_h)
  97     TopSmallWallsPlan();
  98   linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
  99     TopCeilPlan();
 100   linextr(-board_th, usb_wall_h)
 101     TopMainWallsPlan();
 102 }
 103
 104 module Bottom(){ ////toplevel
 105 }