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   1 ;
   2 ; dump
   3 ;
   4 ; Dump a register block
   5 ;
   6 ; © 1994-1998 Straylight
   7 ;
   8
   9 ;----- Licensing note -------------------------------------------------------
  10 ;
  11 ; This file is part of Straylight's core library (corelib).
  12 ;
  13 ; Corelib is free software; you can redistribute it and/or modify
  14 ; it under the terms of the GNU General Public License as published by
  15 ; the Free Software Foundation; either version 2, or (at your option)
  16 ; any later version.
  17 ;
  18 ; Corelib is distributed in the hope that it will be useful,
  19 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 ; GNU General Public License for more details.
  22 ;
  23 ; You should have received a copy of the GNU General Public License
  24 ; along with Corelib.  If not, write to the Free Software Foundation,
  25 ; 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26
  27 ; dump
  28 ;
  29 ; Standard routine - displays contents of a register save block.  May be
  30 ; used in SVC mode.
  31 ;
  32 ; Parameters:     R0 == pointer to block of 16 words, for value of R0-R15
  33 ;                 R1 == pointer to string to display
  34 ;
  35 ; On exit:        Most registers corrupted.
  36 ;
  37 ; Notes:          Use DUMP macro to set up the call.  This will preserve all
  38 ;                 registers and set up the save block etc.  This code will
  39 ;                 be inserted only if necessary.
  40
  41                 ROUT
  42
  43                 [       hdr_incDump
  44
  45 hdr_regDump     MOV     R8,R14                  ;Store link
  46                 SWI     XOS_IntOn
  47                 MOV     R9,R0                   ;Point to reg dump
  48                 MOV     R10,#0                  ;Register number
  49                 SWI     XOS_WriteS              ;Display header
  50                 DCB     6,26,4,12
  51                 DCB     "------------------------------------------"
  52                 DCB     13,10,10
  53                 DCB     "Register dump follows...",0
  54                 ALIGN
  55                 MOV     R0,R1                   ;Show message from macro
  56                 SWI     XOS_Write0              ;Show it
  57                 SWI     XOS_WriteS
  58                 DCB     13,10,10
  59                 DCB     "------------------------------------------"
  60                 DCB     13,10,10,0
  61                 ALIGN
  62 00              ADRL    R0,%f89                 ;Point to reg name table
  63                 ADD     R0,R0,R10,LSL #2        ;Point to correct one
  64                 SWI     XOS_Write0              ;Print on the screen
  65                 SWI     XOS_WriteS              ;Display next bit
  66                 DCB     " == ",0                ;What to display
  67                 ALIGN
  68                 LDR     R0,[R9,R10,LSL #2]      ;Get register contents
  69                 CMP     R10,#15                 ;Is this the PC?
  70                 BICEQ   R0,R0,#&FC000003        ;Yes - clear out PSR
  71                 ADRL    R1,%f88                 ;Buffer
  72                 MOV     R2,#16                  ;Length of buffer
  73                 SWI     XOS_ConvertHex8         ;Convert
  74                 SWI     XOS_Write0              ;Show on screen
  75                 SWI     XOS_NewLine             ;Start a new line
  76                 CMP     R10,#15                 ;Have we finished?
  77                 ADDNE   R10,R10,#1              ;No: move to next register
  78                 BNE     %b00
  79
  80                 SWI     XOS_NewLine
  81                 SWI     XOS_WriteS              ;Display a message
  82                 DCB     "Processor mode: ",0
  83                 ALIGN
  84                 LDR     R7,[R9,R10,LSL #2]      ;Get the number again
  85                 AND     R1,R7,#&3               ;Get the processor mode
  86                 ADR     R0,%f87                 ;Point to message table
  87                 ADD     R0,R0,R1,LSL #2         ;Get appropriate one
  88                 SWI     XOS_Write0
  89                 SWI     XOS_NewLine
  90                 SWI     XOS_WriteS
  91                 DCB     "FIQ ",0
  92                 ALIGN
  93                 TST     R7,#FIQ_disable
  94                 ADREQ   R0,%f85
  95                 ADRNE   R0,%f86
  96                 SWI     XOS_Write0
  97                 SWI     XOS_WriteS
  98                 DCB     "IRQ ",0
  99                 ALIGN
 100                 TST     R7,#IRQ_disable
 101                 ADREQ   R0,%f85
 102                 ADRNE   R0,%f86
 103                 SWI     XOS_Write0
 104                 SWI     XOS_WriteS
 105                 DCB     "Other flags: ",0
 106                 ALIGN
 107                 TST     R7,#N_flag
 108                 MOVEQ   R0,#'n'
 109                 MOVNE   R0,#'N'
 110                 SWI     XOS_WriteC
 111                 TST     R7,#Z_flag
 112                 MOVEQ   R0,#'z'
 113                 MOVNE   R0,#'Z'
 114                 SWI     XOS_WriteC
 115                 TST     R7,#C_flag
 116                 MOVEQ   R0,#'c'
 117                 MOVNE   R0,#'C'
 118                 SWI     XOS_WriteC
 119                 TST     R7,#V_flag
 120                 MOVEQ   R0,#'v'
 121                 MOVNE   R0,#'V'
 122                 SWI     XOS_WriteC
 123                 SWI     XOS_WriteS
 124                 DCB     13,10,10
 125                 DCB     "Press any key to continue execution...",0
 126                 ALIGN
 127                 SWI     XOS_ReadC
 128                 CMP     R0,#17                  ;^Q
 129                 SWIEQ   OS_BreakPt
 130                 MOVS    PC,R8
 131
 132 85
 133                 DCB     "enabled",13,10,0
 134 86
 135                 DCB     "disabled",13,10,0
 136
 137 87
 138                 DCB     "USR",0
 139                 DCB     "FIQ",0
 140                 DCB     "IRQ",0
 141                 DCB     "SVC",0
 142
 143 88
 144                 %       16                      ;Block for translation
 145
 146 89
 147                 DCB     " R0",0
 148                 DCB     " R1",0
 149                 DCB     " R2",0
 150                 DCB     " R3",0
 151                 DCB     " R4",0
 152                 DCB     " R5",0
 153                 DCB     " R6",0
 154                 DCB     " R7",0
 155                 DCB     " R8",0
 156                 DCB     " R9",0
 157                 DCB     "R10",0
 158                 DCB     "R11",0
 159                 DCB     "R12",0
 160                 DCB     "R13",0
 161                 DCB     "R14",0
 162                 DCB     " PC",0
 163                 ALIGN
 164
 165                 ]
 166
 167                 END