chiark / gitweb /
digispark-with-cable: wip
authorIan Jackson <ijackson@chiark.greenend.org.uk>
Mon, 16 Oct 2023 23:18:01 +0000 (00:18 +0100)
committerIan Jackson <ijackson@chiark.greenend.org.uk>
Thu, 26 Oct 2023 17:10:37 +0000 (18:10 +0100)
Signed-off-by: Ian Jackson <ijackson@chiark.greenend.org.uk>
digispark-with-cable.scad

index 09d6466beb53ef88f30ee21bcbfe97ee29e1bf2e..96f56042b64f58a7e9b843f2add9dbf75fef1f79 100644 (file)
@@ -19,6 +19,10 @@ board_th = 1.92 + 0.1;
 sw_to_edge = board_w/2 + 0.1;
 
 front_wall_th = 0.4;
+egress_w = 8.0;
+
+wall_y_min = -board_l - side_wall_th;;
+ceil_y_min = wall_y_min - 5;;
 
 small_walls = [
               [ [0, 0], [-sw_to_edge, -1.0] ],
@@ -50,16 +54,18 @@ module TopCeilPlan() {
     rectfromto([ -usb_w/2,              -0.01        ],
               [ 0.1,                   usb_tongue_d ]);
     rectfromto([ -board_w/2 - side_wall_th, 0            ],
-              [ 0.1,                       -board_l     ]);
+              [ 0.1,                       ceil_y_min   ]);
   }
 }
 module TopMainWallsPlan() {
   BothSides(){
-    rectfromto([ -board_w/2 - side_wall_th, 0            ],
-              [ -board_w/2,                -board_l     ]);
+    rectfromto([ -board_w/2 - side_wall_th, 0          ],
+              [ -board_w/2,                wall_y_min ]);
     rectfromto([ -board_w/2 - side_wall_th, 0             ],
                [ -usb_w/2,                  front_wall_th ]);
   }
+  rectfromto([ -board_w/2 - side_wall_th + egress_w, -board_l   ],
+            [ +board_w/2 + side_wall_th,            wall_y_min ]);
 }
 
 module Top(){