chiark / gitweb /
digispark-with-cable: more space for front tongue
authorIan Jackson <ijackson@chiark.greenend.org.uk>
Tue, 17 Oct 2023 08:20:01 +0000 (09:20 +0100)
committerIan Jackson <ijackson@chiark.greenend.org.uk>
Thu, 26 Oct 2023 17:10:37 +0000 (18:10 +0100)
Signed-off-by: Ian Jackson <ijackson@chiark.greenend.org.uk>
digispark-with-cable.scad

index a597d67d725fd0c972aea06d32cf91155c86ac2e..4416aa8c6b26c5ac7568a8b5e5211d9b23a0dfea 100644 (file)
@@ -7,6 +7,7 @@ include <utils.scad>
 usb_w = 12.01 + 0.19;
 usb_wall_w = 0.51;
 usb_tongue_d = 8.97 - 0.2;
+usb_tongue_w_slop = +0.5;
 usb_wall_h = 4.54 - 2.04;
 usb_ceil_th = 0.425;
 
@@ -40,6 +41,12 @@ module BothSides(){
     }
   }
 }
+module FrontWallsPlan(slop) {
+  BothSides(){
+    rectfromto([ -board_w/2 - side_wall_th,    0             ],
+               [ -usb_w/2 - slop,              front_wall_th ]);
+  }
+}
 module TopSmallWallsPlan() {
   for (m=[0,1]) {
     mirror([m,0]) {
@@ -47,6 +54,7 @@ module TopSmallWallsPlan() {
                 [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
     }
   }
+  FrontWallsPlan(0);
   for (w=small_walls) {
     rectfromto(w[0], w[1]);
   }
@@ -66,9 +74,8 @@ module TopMainWallsPlan() {
   BothSides(){
     rectfromto([ -board_w/2 - side_wall_th, 0          ],
               [ -board_w/2,                wall_y_min ]);
-    rectfromto([ -board_w/2 - side_wall_th, 0             ],
-               [ -usb_w/2,                  front_wall_th ]);
   }
+  FrontWallsPlan(usb_tongue_w_slop);
 //  rectfromto([ -board_w/2 - side_wall_th + egress_w, -board_l   ],
 //          [ +board_w/2 + side_wall_th,            wall_y_min ]);
 }