chiark / gitweb /
digispark-with-cable: from v1
authorIan Jackson <ijackson@chiark.greenend.org.uk>
Tue, 17 Oct 2023 00:37:58 +0000 (01:37 +0100)
committerIan Jackson <ijackson@chiark.greenend.org.uk>
Thu, 26 Oct 2023 17:10:37 +0000 (18:10 +0100)
Signed-off-by: Ian Jackson <ijackson@chiark.greenend.org.uk>
digispark-with-cable.scad

index 3a1a3ad8a5047b8b2738439fe5818e814fc896d8..d13a15c9c758560a618f6d69cfdbde7589aab53d 100644 (file)
@@ -30,6 +30,8 @@ small_walls = [
               [ [3.0, -11.72] ,[sw_to_edge, -13.38] ],
               [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
               ];
+chip_cutout = [[ -sw_to_edge + 4.20,    -4.50 ],
+              [ -sw_to_edge + 11.95,  -11.90 ]];
 
 module BothSides(){
   for (m=[0,1]) {
@@ -50,11 +52,14 @@ module TopSmallWallsPlan() {
   }
 }
 module TopCeilPlan() {
-  BothSides(){
-    rectfromto([ -usb_w/2,              -0.01        ],
-              [ 0.1,                   usb_tongue_d ]);
-    rectfromto([ -board_w/2 - side_wall_th, 0            ],
-              [ 0.1,                       ceil_y_min   ]);
+  difference(){
+    BothSides(){
+      rectfromto([ -usb_w/2,              -0.01        ],
+                [ 0.1,                   usb_tongue_d ]);
+      rectfromto([ -board_w/2 - side_wall_th, 0            ],
+                [ 0.1,                       ceil_y_min   ]);
+    }
+    rectfromto(chip_cutout[0], chip_cutout[1]);
   }
 }
 module TopMainWallsPlan() {