5 //tongue_w = 11.92 + 0.4;
8 usb_wall_w = 0.75 - 0.1;
9 usb_tongue_d = 8.97 - 0.2;
10 usb_wall_h = 4.54 - 2.04;
15 board_l = 17.56 + 0.2;
16 board_w = 19.14 + 0.2;
17 board_th = 1.92 + 0.1;
19 sw_to_edge = board_w/2 + 0.1;
24 wall_y_min = -board_l - side_wall_th;;
25 ceil_y_min = wall_y_min - 5;;
28 [ [0, 0], [-sw_to_edge, -1.0] ],
29 [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
30 [ [3.0, -11.72] ,[sw_to_edge, -13.38] ],
31 [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
33 chip_cutout = [[ -sw_to_edge + 4.20, -4.50 ],
34 [ -sw_to_edge + 11.95, -11.90 ]];
43 module TopSmallWallsPlan() {
46 rectfromto([ -usb_w/2, -0.01 ],
47 [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
51 rectfromto(w[0], w[1]);
54 module TopCeilPlan() {
57 rectfromto([ -usb_w/2, -0.01 ],
58 [ 0.1, usb_tongue_d ]);
59 rectfromto([ -board_w/2 - side_wall_th, 0 ],
62 rectfromto(chip_cutout[0], chip_cutout[1]);
65 module TopMainWallsPlan() {
67 rectfromto([ -board_w/2 - side_wall_th, 0 ],
68 [ -board_w/2, wall_y_min ]);
69 rectfromto([ -board_w/2 - side_wall_th, 0 ],
70 [ -usb_w/2, front_wall_th ]);
72 rectfromto([ -board_w/2 - side_wall_th + egress_w, -board_l ],
73 [ +board_w/2 + side_wall_th, wall_y_min ]);
77 linextr(0, usb_wall_h)
79 linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
81 linextr(-board_th, usb_wall_h)