5 //tongue_w = 11.92 + 0.4;
9 usb_tongue_d = 8.97 - 0.2;
10 usb_tongue_w_slop = +0.5;
11 usb_wall_h = 4.54 - 2.04;
16 board_l = 17.56 + 0.2;
17 board_w = 19.14 + 0.2;
18 board_th = 1.92 + 0.1;
20 sw_to_edge = board_w/2 + 0.1;
25 wall_y_min = -board_l - side_wall_th;;
26 ceil_y_min = wall_y_min - 5;;
29 [ [0, 0], [-sw_to_edge, -1.0] ],
30 [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
31 // [ [3.0, -11.72], [sw_to_edge, -13.38] ],
32 [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
34 chip_cutout = [[ -sw_to_edge + 4.20, -3.75 ],
35 [ -sw_to_edge + 11.95, -11.90 ]];
44 module FrontWallsPlan(slop) {
46 rectfromto([ -board_w/2 - side_wall_th, 0 ],
47 [ -usb_w/2 - slop, front_wall_th ]);
50 module TopSmallWallsPlan() {
53 rectfromto([ -usb_w/2, -0.01 ],
54 [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
59 rectfromto(w[0], w[1]);
62 module TopCeilPlan() {
65 rectfromto([ -usb_w/2, -0.01 ],
66 [ 0.1, usb_tongue_d ]);
67 rectfromto([ -board_w/2 - side_wall_th, 0 ],
70 rectfromto(chip_cutout[0], chip_cutout[1]);
73 module TopMainWallsPlan() {
75 rectfromto([ -board_w/2 - side_wall_th, 0 ],
76 [ -board_w/2, wall_y_min ]);
78 FrontWallsPlan(usb_tongue_w_slop);
79 rectfromto([ -board_w/2 - side_wall_th + 0, - board_l ],
80 [ +board_w/2 + side_wall_th, wall_y_min ]);
84 linextr(0, usb_wall_h)
86 linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
88 linextr(-board_th, usb_wall_h)