digispark-with-cable.scad

   1 // -*- C -*-
   2
   3 include <utils.scad>
   4
   5 //tongue_w = 11.92 + 0.4;
   6
   7 usb_w = 12.01 - 0.3;
   8 usb_wall_w = 0.75 - 0.1;
   9 usb_tongue_d = 8.97 - 0.2;
  10 usb_wall_h = 4.54 - 2.04;
  11 usb_ceil_th = 0.425;
  12
  13 side_wall_th = 1.5;
  14
  15 board_l = 17.56 + 0.2;
  16 board_w = 19.14 + 0.2;
  17 board_th = 1.92 + 0.1;
  18
  19 sw_to_edge = board_w/2 + 0.1;
  20
  21 front_wall_th = 0.4;
  22 egress_w = 8.0;
  23
  24 wall_y_min = -board_l - side_wall_th;;
  25 ceil_y_min = wall_y_min - 5;;
  26
  27 small_walls = [
  28                [ [0, 0], [-sw_to_edge, -1.0] ],
  29                [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
  30                [ [3.0, -11.72] ,[sw_to_edge, -13.38] ],
  31                [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
  32                ];
  33
  34 module BothSides(){
  35   for (m=[0,1]) {
  36     mirror([m,0]) {
  37       children();
  38     }
  39   }
  40 }
  41 module TopSmallWallsPlan() {
  42   for (m=[0,1]) {
  43     mirror([m,0]) {
  44       rectfromto([ -usb_w/2,              -0.01        ],
  45                  [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
  46     }
  47   }
  48   for (w=small_walls) {
  49     rectfromto(w[0], w[1]);
  50   }
  51 }
  52 module TopCeilPlan() {
  53   BothSides(){
  54     rectfromto([ -usb_w/2,              -0.01        ],
  55                [ 0.1,                   usb_tongue_d ]);
  56     rectfromto([ -board_w/2 - side_wall_th, 0            ],
  57                [ 0.1,                       ceil_y_min   ]);
  58   }
  59 }
  60 module TopMainWallsPlan() {
  61   BothSides(){
  62     rectfromto([ -board_w/2 - side_wall_th, 0          ],
  63                [ -board_w/2,                wall_y_min ]);
  64     rectfromto([ -board_w/2 - side_wall_th, 0             ],
  65                [ -usb_w/2,                  front_wall_th ]);
  66   }
  67   rectfromto([ -board_w/2 - side_wall_th + egress_w, -board_l   ],
  68              [ +board_w/2 + side_wall_th,            wall_y_min ]);
  69 }
  70
  71 module Top(){
  72   linextr(0, usb_wall_h)
  73     TopSmallWallsPlan();
  74   linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
  75     TopCeilPlan();
  76   linextr(-board_th, usb_wall_h)
  77     TopMainWallsPlan();
  78 }
  79
  80 Top();