chiark / gitweb /
digispark-with-cable: wip
[reprap-play.git] / digispark-with-cable.scad
1 // -*- C -*-
2
3 include <utils.scad>
4
5 //tongue_w = 11.92 + 0.4;
6
7 usb_w = 12.01 - 0.3;
8 usb_wall_w = 0.75 - 0.1;
9 usb_tongue_d = 8.97 - 0.2;
10 usb_wall_h = 4.54 - 2.04;
11 usb_ceil_th = 0.125;
12
13 side_wall_th = 1.5;
14
15 board_l = 17.56 + 0.2;
16 board_w = 19.14 + 0.2;
17 board_th = 1.92 + 0.1;
18
19 sw_to_edge = board_w/2 + 0.1;
20
21 front_wall_th = 0.4;
22
23 small_walls = [
24                [ [0, 0], [-sw_to_edge, -1.0] ],
25                [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
26                [ [3.0, -11.72] ,[sw_to_edge, -13.38] ],
27                [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
28                ];
29
30 module BothSides(){
31   for (m=[0,1]) {
32     mirror([m,0]) {
33       children();
34     }
35   }
36 }
37 module TopSmallWallsPlan() {
38   for (m=[0,1]) {
39     mirror([m,0]) {
40       rectfromto([ -usb_w/2,              -0.01        ],
41                  [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
42     }
43   }
44   for (w=small_walls) {
45     rectfromto(w[0], w[1]);
46   }
47 }
48 module TopCeilPlan() {
49   BothSides(){
50     rectfromto([ -usb_w/2,              -0.01        ],
51                [ 0.1,                   usb_tongue_d ]);
52     rectfromto([ -board_w/2 - side_wall_th, 0            ],
53                [ 0.1,                       -board_l     ]);
54   }
55 }
56 module TopMainWallsPlan() {
57   BothSides(){
58     rectfromto([ -board_w/2 - side_wall_th, 0            ],
59                [ -board_w/2,                -board_l     ]);
60     rectfromto([ -board_w/2 - side_wall_th, 0             ],
61                [ -usb_w/2,                  front_wall_th ]);
62   }
63 }
64
65 module Top(){
66   linextr(0, usb_wall_h)
67     TopSmallWallsPlan();
68   linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
69     TopCeilPlan();
70   linextr(-board_th, usb_wall_h)
71     TopMainWallsPlan();
72 }
73
74 Top();