digispark-with-cable.scad

   1 // -*- C -*-
   2
   3 include <utils.scad>
   4
   5 //tongue_w = 11.92 + 0.4;
   6
   7 usb_w = 12.01 + 0.19;
   8 usb_wall_w = 0.51;
   9 usb_tongue_d = 8.97 - 0.2;
  10 usb_tongue_w_slop = +0.5;
  11 usb_wall_h = 4.54 - 2.04;
  12 usb_ceil_th = 0.425;
  13
  14 side_wall_th = 1.5;
  15
  16 board_l = 17.56 + 0.2;
  17 board_w = 19.14 + 0.2;
  18 board_th = 1.92 + 0.1;
  19
  20 sw_to_edge = board_w/2 + 0.1;
  21
  22 front_wall_th = 0.75;
  23 // egress_w = 8.0;
  24
  25 wall_y_min = -board_l - side_wall_th;;
  26 ceil_y_min = wall_y_min - 5;;
  27
  28 small_walls = [
  29                [ [0, 0], [-sw_to_edge, -1.0] ],
  30                [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
  31 //             [ [3.0, -11.72],              [sw_to_edge, -13.38] ],
  32                [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
  33                ];
  34 chip_cutout = [[ -sw_to_edge + 4.20,    -3.75 ],
  35                [ -sw_to_edge + 11.95,  -11.90 ]];
  36
  37 module BothSides(){
  38   for (m=[0,1]) {
  39     mirror([m,0]) {
  40       children();
  41     }
  42   }
  43 }
  44 module FrontWallsPlan(slop) {
  45   BothSides(){
  46     rectfromto([ -board_w/2 - side_wall_th,    0             ],
  47                [ -usb_w/2 - slop,              front_wall_th ]);
  48   }
  49 }
  50 module TopSmallWallsPlan() {
  51   for (m=[0,1]) {
  52     mirror([m,0]) {
  53       rectfromto([ -usb_w/2,              -0.01        ],
  54                  [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
  55     }
  56   }
  57   FrontWallsPlan(0);
  58   for (w=small_walls) {
  59     rectfromto(w[0], w[1]);
  60   }
  61 }
  62 module TopCeilPlan() {
  63   difference(){
  64     BothSides(){
  65       rectfromto([ -usb_w/2,              -0.01        ],
  66                  [ 0.1,                   usb_tongue_d ]);
  67       rectfromto([ -board_w/2 - side_wall_th, 0            ],
  68                  [ 0.1,                       ceil_y_min   ]);
  69     }
  70     rectfromto(chip_cutout[0], chip_cutout[1]);
  71   }
  72 }
  73 module TopMainWallsPlan() {
  74   BothSides(){
  75     rectfromto([ -board_w/2 - side_wall_th, 0          ],
  76                [ -board_w/2,                wall_y_min ]);
  77   }
  78   FrontWallsPlan(usb_tongue_w_slop);
  79 //  rectfromto([ -board_w/2 - side_wall_th + egress_w, -board_l   ],
  80 //           [ +board_w/2 + side_wall_th,            wall_y_min ]);
  81 }
  82
  83 module Top(){
  84   linextr(0, usb_wall_h)
  85     TopSmallWallsPlan();
  86   linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
  87     TopCeilPlan();
  88   linextr(-board_th, usb_wall_h)
  89     TopMainWallsPlan();
  90 }
  91
  92 Top();