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bb52c31)
I don't expect ARM64 processors to omit the SIMD instructions, but it's
convenient to have a way to inhibit the accelerated code (e.g., for
performance measurement).
cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
#if CPUFAM_ARM64
cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
#if CPUFAM_ARM64
- DISPATCH_PICK_COND(mpmont_reduce, maybe_redc4_arm64_simd, 1);
+ DISPATCH_PICK_COND(mpmont_reduce, maybe_redc4_arm64_simd,
+ cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
DISPATCH_PICK_FALLBACK(mpmont_reduce, simple_redccore);
}
#endif
DISPATCH_PICK_FALLBACK(mpmont_reduce, simple_redccore);
}
cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
#if CPUFAM_ARM64
cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
#if CPUFAM_ARM64
- DISPATCH_PICK_COND(mpmont_mul, maybe_mul4_arm64_simd, 1);
+ DISPATCH_PICK_COND(mpmont_mul, maybe_mul4_arm64_simd,
+ cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
DISPATCH_PICK_FALLBACK(mpmont_mul, simple_mulcore);
}
#endif
DISPATCH_PICK_FALLBACK(mpmont_mul, simple_mulcore);
}
cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
#if CPUFAM_ARM64
cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
#if CPUFAM_ARM64
- DISPATCH_PICK_COND(mpx_umul, maybe_umul4_arm64_simd, 1);
+ DISPATCH_PICK_COND(mpx_umul, maybe_umul4_arm64_simd,
+ cpu_feature_p(CPUFEAT_ARM_NEON));
#endif
DISPATCH_PICK_FALLBACK(mpx_umul, simple_umul);
}
#endif
DISPATCH_PICK_FALLBACK(mpx_umul, simple_umul);
}