From b04d4da625bee2840fe92d262abcd7e1fffc3d08 Mon Sep 17 00:00:00 2001
From: ian <ian>
Date: Wed, 24 Mar 2004 01:00:55 +0000
Subject: [PATCH] spice stuff

---
 .cvsignore         |  4 +++
 spice/booster.cir  | 74 ++++++++++++++++++++++++++++++++++++++++++++++
 spice/opmodel1.cir | 17 +++++++++++
 spice/opmodmac.cir | 27 +++++++++++++++++
 4 files changed, 122 insertions(+)
 create mode 100644 spice/booster.cir
 create mode 100644 spice/opmodel1.cir
 create mode 100644 spice/opmodmac.cir

diff --git a/.cvsignore b/.cvsignore
index c7c524f..fa3989b 100644
--- a/.cvsignore
+++ b/.cvsignore
@@ -6,3 +6,7 @@ testjoin
 *.ps
 *.d4
 *.new
+*,*.gnuplot-data
+*,*.gnuplot-cmd
+*,gnuplot-fifo
+*.gnuplots.sh
diff --git a/spice/booster.cir b/spice/booster.cir
new file mode 100644
index 0000000..63b2708
--- /dev/null
+++ b/spice/booster.cir
@@ -0,0 +1,74 @@
+BOOSTER.CIR - BOOSTER AND POWER COMPENSATOR
+.< opmodmac.cir
+.model bat86 d eg=0.69
+.model 1n4148 d
+.model zenforwards d
+.model zenbackwards d
+.model spp42n03s2l nmos level=1
+*
+* input stage
+v18		10 0	18
+v12		1 0	12
+
+rdropfake	10 11	0.01
+*mdrop		10 42 11 11	spp42n03s2l
+
+cbypass		11 0	1u
+* lmd18200t
+rswah		11 30	pulse	1m 0.3	2u 1u 1u 46u 100u
+rswbl		20 0	pulse	1m 0.3	2u 1u 1u 46u 100u
+rswal		30 0	pulse	1m 0.3	52u 1u 1u 46u 100u
+rswbh		11 20	pulse	1m 0.3	52u 1u 1u 46u 100u
+
+* output sensor
+rminload	20 30	330
+
+dsensebh	20 21	bat86
+dsenseah	30 21	bat86
+dsensebl	31 20	bat86
+dsenseal	31 30	bat86
+
+* resistor network (high side)
+rinh		21 22	5.1k
+dinh		22 1	1n4148
+rinh2		22 23	2.4k
+rinhdo		23 24	3.0k
+rinhdh		1 27	2.0k
+rinhdth		27 24	0.5k
+rinhdtl		24 26	0.5k
+rinhdl		26 0	910
+
+* resistor network (low side)
+rinl		31 32	6.2k
+dinlf		0 32	zenforwards
+dinlb		32 325	zenbackwards
+vdinlb		325 0	7.8
+rinl2		32 33	1.3k
+rinlu		1 33	3.9k
+rfeedback	40 33	2.5meg
+
+* op-amp
+x271		23 33 41 0 1	opamp1
+
+* results
+*.print	tran	v(11) v(20) v(30) v(21) v(31) v(23) v(33) v(41)
+.print	tran	v(11) v(20) v(30) v(21) v(22) v(23) v(24) v(26) v(27)
+.probe
+.tran	0 5u 100n
+.end
+
+* output/driver network
+rorc		40 41	10.0k
+corc		41 0	220n
+dosuf		41 42	zenforwards
+dosub		42 415	zenbackwards
+vdosub		415 41	8.6
+ropu		10 42	330k
+dlim1		42 43	1n4148
+dlim2f		11 43	zenforwards
+dlim2b		43 435	zenbackwards
+vdlim2b		435 11	5.1
+* results
+.print	tran	v(11) v(20) v(30) v(40) v(41)
+.probe
+.tran	0 200u 10n
diff --git a/spice/opmodel1.cir b/spice/opmodel1.cir
new file mode 100644
index 0000000..f546a27
--- /dev/null
+++ b/spice/opmodel1.cir
@@ -0,0 +1,17 @@
+OPMODEL1.CIR -OPAMP MODEL SINGLE-POLE 
+*
+vpp	10	0	10
+vmm	0	90	10
+
+VS      1       0       AC      1
+XOP     1 0     3   90 10    OPAMP1
+RL      3       0       1K
+*
+.< opmodmac.cir
+* 
+* VIEW RESULTS
+.PRINT   AC      VM(3)
+* ANALYSIS
+.PROBE
+.AC     DEC     5 1 100MEG
+.END
diff --git a/spice/opmodmac.cir b/spice/opmodmac.cir
new file mode 100644
index 0000000..4af5bc0
--- /dev/null
+++ b/spice/opmodmac.cir
@@ -0,0 +1,27 @@
+OPAMP MACRO MODEL, SINGLE-POLE 
+* connections:      non-inverting input    gnd
+*                   |   inverting input    |    vcc 
+*                   |   |   output         |    |
+*                   |   |   |              |    |
+.SUBCKT OPAMP1      1   2   6              20   40
+* INPUT IMPEDANCE
+RIN     1       2       10MEG
+* DC GAIN=100K AND POLE1=100HZ
+* UNITY GAIN = DCGAIN X POLE1 = 10MHZ
+EGAIN   3 0     1 2     100K
+RP1     3       4       1K
+CP1     4       0       1.5915UF
+* centralise and clamp
+rclah	40	30	10k
+rclal	30	20	10k
+eclamp	31	30	4 0 1
+.model diode d
+vclamph	40	39	1.5
+vclampl 21	20	1.5
+dclamph	31	39	diode
+dclampl 21	31	diode
+* OUTPUT BUFFER AND RESISTANCE
+EBUFFER 5 0     31 0	1
+*EBUFFER 5 0     4 0	1
+ROUT    5       6       10
+.ENDS
-- 
2.30.2