From: ian <ian>
Date: Wed, 24 Mar 2004 01:42:29 +0000 (+0000)
Subject: opamp model is crap
X-Git-Url: https://www.chiark.greenend.org.uk/ucgi/~ijackson/git?a=commitdiff_plain;h=fd90d38f5ebb5eacb5a35ed0f275289f86eaccc7;p=trains.git

opamp model is crap
---

diff --git a/spice/booster.cir b/spice/booster.cir
index 63b2708..3495521 100644
--- a/spice/booster.cir
+++ b/spice/booster.cir
@@ -48,13 +48,12 @@ rinlu		1 33	3.9k
 rfeedback	40 33	2.5meg
 
 * op-amp
-x271		23 33 41 0 1	opamp1
+x271		23 33 41 0 1	1000 1001	opamp1
 
 * results
-*.print	tran	v(11) v(20) v(30) v(21) v(31) v(23) v(33) v(41)
-.print	tran	v(11) v(20) v(30) v(21) v(22) v(23) v(24) v(26) v(27)
+.print	tran	v(11) v(20) v(30) v(21) v(31) v(23) v(33) v(41)
 .probe
-.tran	0 5u 100n
+.tran	0 100u 100n
 .end
 
 * output/driver network
diff --git a/spice/opmodel1.cir b/spice/opmodel1.cir
index f546a27..d93770a 100644
--- a/spice/opmodel1.cir
+++ b/spice/opmodel1.cir
@@ -3,7 +3,7 @@ OPMODEL1.CIR -OPAMP MODEL SINGLE-POLE
 vpp	10	0	10
 vmm	0	90	10
 
-VS      1       0       AC      1
+VS      1       0       AC      1	else  sin(0voff 1vpeak 2khz)
 XOP     1 0     3   90 10    OPAMP1
 RL      3       0       1K
 *
@@ -11,7 +11,9 @@ RL      3       0       1K
 * 
 * VIEW RESULTS
 .PRINT   AC      VM(3)
+.PRINT   tran    v(1) V(3)
 * ANALYSIS
 .PROBE
 .AC     DEC     5 1 100MEG
+.TRAN 	5US  500US
 .END
diff --git a/spice/opmodmac.cir b/spice/opmodmac.cir
index 4af5bc0..ff930c2 100644
--- a/spice/opmodmac.cir
+++ b/spice/opmodmac.cir
@@ -3,25 +3,25 @@ OPAMP MACRO MODEL, SINGLE-POLE
 *                   |   inverting input    |    vcc 
 *                   |   |   output         |    |
 *                   |   |   |              |    |
-.SUBCKT OPAMP1      1   2   6              20   40
+.SUBCKT OPAMP1      1   2   6              20   40  3	4
 * INPUT IMPEDANCE
 RIN     1       2       10MEG
 * DC GAIN=100K AND POLE1=100HZ
-* UNITY GAIN = DCGAIN X POLE1 = 10MHZ
-EGAIN   3 0     1 2     100K
-RP1     3       4       1K
-CP1     4       0       1.5915UF
-* centralise and clamp
+* gain, centralise and clamp
 rclah	40	30	10k
 rclal	30	20	10k
-eclamp	31	30	4 0 1
+ecent	31	30	1 2	 30k
 .model diode d
 vclamph	40	39	1.5
 vclampl 21	20	1.5
 dclamph	31	39	diode
 dclampl 21	31	diode
+
+* first pole: UNITY GAIN = DCGAIN X POLE1 = 10MHZ
+epole   3 0    31 0     1
+RP1     3       4       10
+CP1     4       0       1.5915UF
 * OUTPUT BUFFER AND RESISTANCE
-EBUFFER 5 0     31 0	1
-*EBUFFER 5 0     4 0	1
+EBUFFER 5 0     4 0	1
 ROUT    5       6       10
 .ENDS