From: ian Date: Wed, 24 Mar 2004 21:57:24 +0000 (+0000) Subject: before try ngspice X-Git-Url: https://www.chiark.greenend.org.uk/ucgi/~ijackson/git?a=commitdiff_plain;h=4a1bff64d00528a09e20218d0552bcb505638974;p=trains.git before try ngspice --- diff --git a/spice/booster.cir b/spice/booster.cir index f163bfa..5ca414f 100644 --- a/spice/booster.cir +++ b/spice/booster.cir @@ -1,6 +1,6 @@ BOOSTER.CIR - BOOSTER AND POWER COMPENSATOR -.< opmodmac.cir -.< lf356.mod +.include opmodmac.cir +.include lf356.mod .model bat86 d eg=0.69 .model 1n4148 d .model zenforwards d @@ -53,23 +53,23 @@ x356 23 33 1 0 40 lf356/ns *x271 23 33 41 0 1 1000 1001 opamp1 * results +.tran 0 10u 100n .print tran v(10) v(11) v(20) v(30) v(40) v(23) v(33) .probe -.tran 0 10u 100n .end - -* output/driver network -rorc 40 41 10.0k -corc 41 0 220n -dosuf 41 42 zenforwards -dosub 42 415 zenbackwards -vdosub 415 41 8.6 -ropu 10 42 330k -dlim1 42 43 1n4148 -dlim2f 11 43 zenforwards -dlim2b 43 435 zenbackwards -vdlim2b 435 11 5.1 -* results -.print tran v(11) v(20) v(30) v(40) v(41) -.probe -.tran 0 200u 10n +* +* * output/driver network +* rorc 40 41 10.0k +* corc 41 0 220n +* dosuf 41 42 zenforwards +* dosub 42 415 zenbackwards +* vdosub 415 41 8.6 +* ropu 10 42 330k +* dlim1 42 43 1n4148 +* dlim2f 11 43 zenforwards +* dlim2b 43 435 zenbackwards +* vdlim2b 435 11 5.1 +* * results +* .print tran v(11) v(20) v(30) v(40) v(41) +* .probe +* .tran 0 200u 10n diff --git a/spice/opmodel1.cir b/spice/opmodel1.cir index 7dec4bd..8e6d5b7 100644 --- a/spice/opmodel1.cir +++ b/spice/opmodel1.cir @@ -1,12 +1,14 @@ OPMODEL1.CIR -OPAMP MODEL SINGLE-POLE * -.< lf356.mod +.include opmodmac.cir vpp 10 0 10 vmm 0 90 10 -VS 1 0 AC 1 else sin(0voff 1vpeak 2khz) -XOP 1 0 3 90 10 lf356/ns +VS 1 0 ac 1 +* dc 1 AC 1 else sin(0voff 1vpeak 2khz) +*XOP 1 0 3 90 10 +XOP 1 0 3 90 10 opamp1 RL 3 0 1K * * diff --git a/spice/opmodmac.cir b/spice/opmodmac.cir index ff930c2..b53bc63 100644 --- a/spice/opmodmac.cir +++ b/spice/opmodmac.cir @@ -3,7 +3,8 @@ OPAMP MACRO MODEL, SINGLE-POLE * | inverting input | vcc * | | output | | * | | | | | -.SUBCKT OPAMP1 1 2 6 20 40 3 4 +.SUBCKT OPAMP1 1 2 6 20 40 +*3 4 * INPUT IMPEDANCE RIN 1 2 10MEG * DC GAIN=100K AND POLE1=100HZ diff --git a/spice/test.cir b/spice/test.cir new file mode 100644 index 0000000..36838f6 --- /dev/null +++ b/spice/test.cir @@ -0,0 +1,31 @@ +OPMODEL1.CIR - OPAMP MODEL SINGLE-POLE +* +* OPAMP MACRO MODEL, SINGLE-POLE +* connections: non-inverting input +* | inverting input +* | | output +* | | | +.SUBCKT OPAMP1 1 2 6 +* INPUT IMPEDANCE +RIN 1 2 10MEG +* DC GAIN=100K AND POLE1=100HZ +* UNITY GAIN = DCGAIN X POLE1 = 10MHZ +EGAIN 3 0 1 2 100K +RP1 3 4 1K +CP1 4 0 1.5915UF +* OUTPUT BUFFER AND RESISTANCE +EBUFFER 5 0 4 0 1 +ROUT 5 6 10 +.ENDS +* +VS 1 0 AC 1 +XOP 1 0 3 OPAMP1 +RL 3 0 1K +* +* ANALYSIS +.AC DEC 5 1 100MEG +* VIEW RESULTS +*.PLOT AC VM(3) +.print AC VM(3) vp(3) +.PROBE +.END