From: ian <ian>
Date: Fri, 26 Mar 2004 23:28:42 +0000 (+0000)
Subject: switches
X-Git-Url: https://www.chiark.greenend.org.uk/ucgi/~ijackson/git?a=commitdiff_plain;h=254375e968a144b0d2e3a5d600fe6e35cbb9e523;p=trains.git

switches
---

diff --git a/spice/booster.cir b/spice/booster.cir
index e14574e..620d3a3 100644
--- a/spice/booster.cir
+++ b/spice/booster.cir
@@ -18,18 +18,27 @@ v12		1 0	12
 xmdrop		11 42 10	irf5305
 
 cbypass		11 0	1u
+*csmooth		11 0	100u
+
 * lmd18200t
-vgoahbl		0 311	pulse(	1meg 1 52u 1u 1u 46u 100u )
-vgoalbh		0 211	pulse(	1meg 1  2u 1u 1u 46u 100u )
+vgoahbl		311 0	pulse(	0 1 52u 1u 1u 46u 100u )
+vgoalbh		211 0	pulse(	0 1  2u 1u 1u 46u 100u )
 
-bswah		11 30	i=v(11,30)/v(0,311)
-bswbl		20 0	i=v(20,0)/v(0,311)
-bswal		30 0	i=v(30,0)/v(0,211)
-bswbh		11 20	i=v(11,20)/v(0,211)
+.model slmd18200t sw (vt=0.5 vh=0.1 ron=1 roff=1meg)
+sswah		11 30	311 0	slmd18200t	on
+sswbl		20 0	311 0	slmd18200t	on
+sswal		30 0	211 0	slmd18200t	off
+sswbh		11 20	211 0	slmd18200t	off
 
-* output sensor
 rminload	20 30	330
-*rload		20 30	330
+
+.model sload sw (vt=0.5 vh=0.1 ron=6 roff=1meg)
+vgoload		411 0	pulse(1 0 3.141592m 1u 1u 10.141592m 18.283184m)
+sload		20 30	411 0	sload
+
+* output sensor
+*rload		20 30	6
+*rload		20 30	90
 
 xdsensebh	20 21	bat85
 xdsenseah	30 21	bat85
@@ -51,25 +60,29 @@ rinl		31 32	6.2k
 xzinl		0 32	bzx55-c8v2
 rinl2		32 33	1.3k
 rinlu		1 33	3.9k
-rfeedback	40 33	2.5meg
+*rfeedback	40 33	2.5meg
 
 * op-amp
 x356		23 33  1 0  40	lf356/ns
 
 * output/driver network
-rorc		40 41	10k
-corc		41 0	1u
+rorc		40 41	2k
+*corc		41 0	1u
+ropu		10 42	2k
+
+cgateplus	11 42	470n
+
 *xzosuf		41 42	bzx55-c9v1
-xzosuf		41 42	bzx55-c10
+*xzosuf		41 42	bzx55-c10
 *xzosuf		41 42	bzx55-c5v6
+xzosuf		41 42	bzx55-c7v5
 *xzosuf		41 42	bzx55-c2v4
-ropu		10 42	300k
 *dlim1		42 43	1n4148
 *xzlim2		11 43	bzx55-c5v6
 
 * results
-.tran	100n 10m
-.print	tran	v(11) v(20) v(30) v(31) v(32) v(33) v(40) v(42)
+.tran	300n 20m
+.print	tran	v(11) v(20) v(30) v(40) v(41) v(42)
 *.print	tran	v(11) v(20) v(30) v(21) v(22) v(23) v(24) v(1) v(27) v(24) v(26)
 *.print	tran	v(11) v(20) v(30) v(23) v(33) v(40) v(41) v(42)
 *.print	tran	v(1) v(23) v(33) v(40) v(10) v(42) v(11) v(20) v(30)