#!/usr/bin/perl
-die unless @ARGV==0 || @ARGV==1 && $ARGV[0] eq 'reversers.net-info';
+# script for expanding condensed netlist format
+
+# Syntax:
+#
+# netspec Type CHIP-pin ...
+#
+# CHIP npins ...pin-spec-item...
+# ...pin-spec-item...
+# defines some pins from CHIP which has pins 1..npins
+#
+# minline-maxline/perchip CHIP pins ...pin-spec-item...
+# ...pin-spec-item...
+# Defines some pins from several chips. See assignpins_multi comment.
+#
+# !PIC picpinlist
+# Defines PIC pins - see assignpicpins
+
+# CHIP is [A-Z][A-Z0-9]*
+#
+# netspec is net[,net]* and indicates that all the nets are aliases for same
+# net even if not mentioned together anywhere else
+#
+# net is [a-z][a-z0-9_]*
+#
+# pin-spec-item is one of
+#
+# netspec assigns next pin to netspec
+#
+# net\d+..\d+ assigns next several pins to sequentially named nets
+# nets will be net\d+ where numbers will go from first
+# \d+ to 2nd \d+ in pin-spec-item inclusive (whether
+# up or down)
+#
+# pin asserts that next pin number to assign would be pin
+#
+# :start[step][%jump/modulo]
+# specifies that the next pin to assign will be start,
+# and what the following pin will be to assign, and so
+# on in arithmetic sequence indefinitely until the
+# next :start[... etc.
+# start can be pin (meaning to start with pin)
+# or -backpin meaning to start with npins-backpin
+# step can be + or - to indicate +1 or -1 or
+# a possibly negative number
+# %jump/modulo means don't generate a simple
+# arithmetic sequence; instead, generate
+# modulo arithmetic sequences starting at
+# start, start+jump, ... start+(modulo-1)*jump
+# and then interleave the sequences to
+# generate the sequence of pins to assign
+
+die if $ARGV[0] =~ m/^\-/;
sub o ($$$@) {
my ($netname, $type, $fmt, @stuff) = @_;
}
sub definepicpins (@) {
- my (@l) = unpack_iter_list(40,'o',@_);
+ die if defined $numpicpins;
+ die unless @_;
+ $numpicpins = shift @_;
+ my (@l) = unpack_iter_list($numpicpins,'o',@_);
my ($i);
local ($_);
for ($i=1; $i<@l; $i++) {
}
}
-definepicpins(qw(1 mclr
- 2 RA0..5 RE0..2
- 11 l_vcc l_gnd clock
- 14 RA6 RC0..3 RD0 RD1
- 21 RD2 RD3 RC4..7 RD4..7
- 31 l_gnd l_vcc
- 33 RB0..7));
-
sub assignpicpins (@) {
- my (@l) = unpack_iter_list(40,'o',@_);
+ die unless defined $numpicpins;
+ my (@l) = unpack_iter_list($numpicpins,'o',@_);
my ($i, $port);
for ($i=1; $i<@l; $i++) {
$_= $l[$i];
}
}
-assignpicpins(qw(1 mclr
- spare0
- reverse0..2
- sense3
- reverse3..5
- sense2
- l_vcc l_gnd clock
- sense1
- pt17,booster_dirn
- pt16,booster_pwm
- sense0
- i2c_clock
- 19 sense5..4
- :40-
- pt1,icsp_pc
- pt0,icsp_pd
- pt6,cdu_enable
- pt7,rs232_fcin
- pt2
- pt8,booster_retry,
- pt9,booster_cutout
- pt10,booster_flag
- l_vcc
- l_gnd
- pt3
- pt11,spare2
- pt12,spare1
- pt4
- pt13,rs232_rxin
- pt14,rs232_txout
- pt15,rs232_fcout
- i2c_data
- pt5
- 21 perpicled));
-
sub assignpins (@) {
my ($name,$pins,@il) = @_;
my ($e);
}
}
-assignpins(qw(BUS 32
- icsp_pdw
- l_gnd icsp_pdrany
- l_gnd icsp_pdrall
- l_gnd clock
- l_gnd l_vcc mclr
- l_gnd i2c_clock led_reflow i2c_data led_refhigh
- rly_gnd rly_v12
- cdu_gnd cdu_out
- )); # 32-way ribbon
-
-@indiv= qw(icsp_pcq l_gnd led_red led_green);
-
-push @indiv, qw(cdu_enable
- booster_retry
- booster_cutout
- booster_flag
- booster_dirn
- booster_pwm
- spare0
- spare1
- spare2
- rs232_rxin
- rs232_txout
- rs232_fcin
- rs232_fcout
- );
-
-assignpins('INDIV0',25, ':1%13/2', @indiv); # 26-way ribbon
-assignpins('INDIV1',26,@indiv); # 25-way D
-
sub assignpins_multi ($$@) {
# Args are linemin linemax linesperchip and a list like for assignpins
# assignpins is done several times to handle all of the lines.
}
}
-assignpins_multi(0,5, 1,
- qw(RLY= 16
- :1 rly_v12
- :4 q=
- :6 qmid=
- :8 t
- :9 qmid=
- :11 t
- :13 t=
- :16 rlydrv=));
-
-assignpins_multi(0,5, 1,
- qw(BR= 4
- :1+2 sshort=*2
- :2 qmid=
- :4 q));
-
-
-foreach $iter (0..5) {
- o("t$iter", Fat, '');
- o("q$iter", Fat, '');
- o("qmid$iter", Fat, '');
-}
-
sub data_fin () {
return if !length $data_accum;
local ($_);
+ my (@s) = split /\s+/, $data_accum;
if ($data_accum =~ s,^(\d+)\-(\d+)/(\d+)\s+,,) {
- assignpins_multi($1,$2,$3, split /\s+/, $data_accum);
+ @s= split /\s+/, $data_accum;
+ assignpins_multi($1,$2,$3, @s);
+ } elsif ($data_accum =~ m/^\!PIC\-ASSIGN\s/) {
+ shift @s;
+ assignpicpins(@s);
+ } elsif ($data_accum =~ m/^\!PIC\-DEFINE\s/) {
+ shift @s;
+ definepicpins(@s);
+ } elsif ($data_accum =~ m/^\!/) {
+ die "bad directive $data_accum";
} else {
- assignpins(split /\s+/, $data_accum);
+ assignpins(@s);
}
undef $data_accum;
}
-while (<DATA>) {
+while (<>) {
next if m/^\#/;
next unless m/\S/;
chomp;
data_fin();
if (m/^([a-z]\S+)\s+(\S+)(\s+(\S.*\S))?$/) {
o($1,$2,"%s",$3);
- } elsif (m/^[A-Z].*/ || m,^\d+\-\d+/\d+\s+[A-Z],) {
+ } elsif (m/^\!?[A-Z].*/ || m,^\d+\-\d+/\d+\s+[A-Z],) {
$data_accum= $_;
} else {
die "$_ ?";
}
foreach $canon (sort keys %propernet) {
+ @stuff= sort { $a cmp $b } split /\s+/, $propernet{$canon}{Stuff};
printf("%s\t%s\t%s\n",
$canon,
$propernet{$canon}{Type},
- $propernet{$canon}{Stuff})
+ join ' ', @stuff)
or die $!;
}
-
-# Syntax:
-#
-# netspec Type CHIP-pin ...
-#
-# CHIP npins ...pin-spec-item...
-# ...pin-spec-item...
-# defines some pins from CHIP which has pins 1..npins
-#
-# minline-maxline/perchip CHIP pins ...pin-spec-item...
-# ...pin-spec-item...
-# Defines some pins from several chips. See assignpins_multi comment.
-#
-# CHIP is [A-Z][A-Z0-9]*
-#
-# netspec is net[,net]* and indicates that all the nets are aliases for same
-# net even if not mentioned together anywhere else
-#
-# net is [a-z][a-z0-9_]*
-#
-# pin-spec-item is one of
-#
-# netspec assigns next pin to netspec
-#
-# net\d+..\d+ assigns next several pins to sequentially named nets
-# nets will be net\d+ where numbers will go from first
-# \d+ to 2nd \d+ in pin-spec-item inclusive (whether
-# up or down)
-#
-# pin asserts that next pin number to assign would be pin
-#
-# :start[step][%jump/modulo]
-# specifies that the next pin to assign will be start,
-# and what the following pin will be to assign, and so
-# on in arithmetic sequence indefinitely until the
-# next :start[... etc.
-# start can be pin (meaning to start with pin)
-# or -backpin meaning to start with npins-backpin
-# step can be + or - to indicate +1 or -1 or
-# a possibly negative number
-# %jump/modulo means don't generate a simple
-# arithmetic sequence; instead, generate
-# modulo arithmetic sequences starting at
-# start, start+jump, ... start+(modulo-1)*jump
-# and then interleave the sequences to
-# generate the sequence of pins to assign
-
-__DATA__
-l_gnd Power
-l_vcc Power
-rly_gnd Power
-rly_v12 Power
-
-TERM 14
- 1 t q
- :3+2 t0..5
- :4+2 q0..5
-
-ULN 18
- :11 rlydrv5..0
- :8- reverse5..0 rly_gnd rly_gnd
- :9 rly_gnd
- :10 rly_v12
-
-CULN 2 rly_gnd rly_v12
-CAC05 2 l_gnd l_vcc
-0-1/1 CPIC= 2 l_gnd l_vcc
-
-RAS 9
- l_vcc
- :2 sense3..0 sense5..4
- - perpicled
-
-0-5/4 OC= 16==8
- :1+2 sensei<..>
- :2+2 q*&
- :-1-2 l_gnd*&
- :-0-2 sense<..>
-
-
-0-5/1 RS= 2
- sensei= qmid=
-
-AC05 14
- :8+
- icsp_pdrall icsp_pdrall_mid icsp_pdrall_mid icsp_pd
- icsp_pdrany icsp_pd
- l_vcc
- :7-
- l_gnd
- icsp_pdw_mid icsp_pdw
- ptgate0 icsp_pd
- - l_gnd
-
-RPDR 2 icsp_pdrall_mid l_vcc
-RPDWU 2 icsp_pdw_mid l_vcc
-RPDWI 2 icsp_pdw_mid icsp_pd
-RPT0U 2 ptgate0 l_vcc
-
-RPCI 2 icsp_pc icsp_pcq
-RPCL 2 icsp_pc l_gnd
-RPCPT 2 icsp_pc ptgate1
-
-0-17/1 PTFET= 3 ptgate= ptdrain= cdu_gnd
-0-17/1 PTD= 2 cdu_out ptdrain=
-2-17/8 RAP= 16 :1 pt<..> :-0- ptgate<..>
-
-POINTS 25
- :25-1%-13/2 ptdrain0..17
-
-
-TS912 8
- :1 ledmid_red perpicled led_reflow
- :7- ledmid_green led_refhigh perpicled
- :4 l_gnd
- :8 l_vcc
-
-RLG 2 ledmid_green led_green
-RLR 2 ledmid_red led_red
-RLL 2 perpicled l_gnd
~ijackson / trains.git / commitdiff