chiark / gitweb /
digispark-with-cable: abolish egress, will do other side
[reprap-play.git] / digispark-with-cable.scad
index 1758a584156d24063de4debb4914670ae35464bf..a597d67d725fd0c972aea06d32cf91155c86ac2e 100644 (file)
@@ -4,7 +4,7 @@ include <utils.scad>
 
 //tongue_w = 11.92 + 0.4;
 
-usb_w = 12.01 - 0.3;
+usb_w = 12.01 + 0.19;
 usb_wall_w = 0.51;
 usb_tongue_d = 8.97 - 0.2;
 usb_wall_h = 4.54 - 2.04;
@@ -19,7 +19,7 @@ board_th = 1.92 + 0.1;
 sw_to_edge = board_w/2 + 0.1;
 
 front_wall_th = 0.75;
-egress_w = 8.0;
+// egress_w = 8.0;
 
 wall_y_min = -board_l - side_wall_th;;
 ceil_y_min = wall_y_min - 5;;
@@ -27,7 +27,7 @@ ceil_y_min = wall_y_min - 5;;
 small_walls = [
               [ [0, 0], [-sw_to_edge, -1.0] ],
               [ [sw_to_edge-4.5, -4.5], [sw_to_edge, -5.7] ],
-              [ [3.0, -11.72],              [sw_to_edge, -13.38] ],
+//            [ [3.0, -11.72],              [sw_to_edge, -13.38] ],
               [ [-sw_to_edge+3.85, -14.90], [sw_to_edge, -13.38] ],
               ];
 chip_cutout = [[ -sw_to_edge + 4.20,    -4.50 ],
@@ -69,8 +69,8 @@ module TopMainWallsPlan() {
     rectfromto([ -board_w/2 - side_wall_th, 0             ],
                [ -usb_w/2,                  front_wall_th ]);
   }
-  rectfromto([ -board_w/2 - side_wall_th + egress_w, -board_l   ],
-            [ +board_w/2 + side_wall_th,            wall_y_min ]);
+//  rectfromto([ -board_w/2 - side_wall_th + egress_w, -board_l   ],
+//          [ +board_w/2 + side_wall_th,            wall_y_min ]);
 }
 
 module Top(){