As we left it last time, we'd designed a simple input port for the podule bus to input up to 15 digital signals.  Let's now expand it to take in a few more basic features.

Address bus

So far, we've completely ignored the address bus.  This means that a read
from any address in our podule space will return the same value.  If we had
some RAM on our podule, only being able to read 16 bits of it would be a
little pointless.  So what to we do with the address bus?

Let's support two input ports, at different addresses.  To do this, we're
going to address decode the LA13 line.  If we remember from last time, we
have 4 Kwords of address space.  A little calculation reveals that LA13 is
the most significant bit of this address - it determines whether we're
accessing the upper or lower 2 Kwords of the total.  Remembering our circuit
from last time (fig 1), what we'd like to do is choose one of these chips
when LA13 is low, and the other when LA13 is high.  To do this, we simply
test LA13 when determining which of two buffer chips to activate (fig 2). 
The buffer chips are as in figure 1, except the /G signals are produced from
the logic in figure 2.

This means that accessing any addresses (if our podule is in slot 0 and we're
using fast IOC mode) between 03340000 and 03341FFC will read the lower
buffer, and between 03342000 and 03343FFC the upper buffer.  We could extend
up to 4096 buffers in this way (but they might not fit on the one PCB!).

Writes

Reads are all very well, but if we actually want to control something (like a
robot, or a hard disc, or a RAM), we need to be able to write as well.  This
is done analogously to reads, using the /IOWR signal.  Figure 3 shows how to
light an LED.  Notice that this uses a 74LS chip rather than a 74HC - mainly
to ensure it can provide enough current for the LED; use of 74LS devices
should be limited to avoid loading the bus unless you want to provide extra
buffering.

The timing diagram for a write can be seen in figure 4.  Essentially this
means the data is available to be grabbed by the podule all the time /PS
is low.  The 74xx273 latches the input D to the output Q in response to a
rising edge on CP.  With the circuit we've used here, CP goes high as soon as
/IOWR and /PS are both low, then falls as soon as one becomes deasserted.  In
this way, the data is clocked into the latch at the start of the cycle and
has the whole cycle to settle into the latch.  Again checking timings we are
allowed 375ns to complete the timing, whilst the 74LS273 takes about 18ns to
propagate - plenty of time!

We can control this LED from the command line (if our podule is in slot 0),
by doing:

*MemoryA b 03340000 <hex value to write>

or in fact to any address in its podule space.  Address decoding as above can
be used to provide more outputs.  As reads and writes don't affect each
other, we can combine the input from figure 1 and the output from figure 3 on
the same board without problems.

Reset

Think about what might happen if, instead of the above circuit driving an
LED, it was used to launch the Space Shuttle (stop laughing, just
imagine...).  When we first turn the computer on, the output is in an
indeterminate state - we don't know whether it's a zero or a one.  This could
be quite embarrassing, if turning our computer on caused an accidental Shuttle
launch.  The podule bus provides for this, by supplying a reset line /RST. 
This goes low when the podule is to be reset on power-on, or when the reset
button is pushed.  In this case, the 74xx273 provides a /MR input, which
resets its outputs to zero when /MR is low.  By connecting /MR to /RST, we
can ensure that the outputs are always low on powerup or reset.  This also
applies to more complex chips (ethernet controllers, serial ports etc) which
need to be in a known state on startup.  As /RST is open-collector, it is
also possible to reset the machine by a podule driving it low.

Read/write

Sometimes we don't want to know when a read or write is happening, we just
want to know which direction it's going in.  If you have an internal bus on
your podule, you might want to copy data from the podule bus to the internal
bus, which looks like a write from the podule bus to your podule.  This can
be done with a gate between the buses, which needs to know the direction of
the transfer.  But if you wait around for /IOWR to 'open the floodgates',
this doesn't leave enough time for the data to settle onto our internal bus
before a chip on our podule tries to store the data - and might end up
storing whatever rubbish happens to be on the bus whilst it's settling.  This
might also happen in the reverse direction.

So we need to know that a) the podule is activated, so we can open the gate between our internal bus and the podule bus, and b) which direction to open the gate in.  We can activate our podule with /PS as we've mentioned before, but we need something to indicate the direction before /IORD or /IOWR come along.  PR/W comes to the rescue.  This is high when a read is
happening and low during a write, and so we can use it to control the flow of
our data. If you have to drive signals to many chips it's typical to use a
74HC245 transceiver to buffer the podule bus in this way, and use this signal
to specify the direction in which to transfer.

RAM example

To round off this article, I'm going to demonstrate interfacing to a more
complex chip than the simple logic we've been using so far.  We're going to
use a 2 KByte static RAM chip to do this.  This may sound quite small, but
it'll usefully demonstrate something next time.

The 6116 is such a beast, having 11 address lines, 8 data lines, /CE (chip
enable), /OE (output enable) and /WE (write enable).  A read can be performed
by dropping /CE, then /OE, then after the access time of the RAM the data is
ready.  This is exactly the same as the read timing diagram from last time!
Similarly, data is written into the RAM on the rising edge of /WE; /CE is
asserted first, then /WE, then the data is latched as /WE rises.  Again, this
is the same as we considered above.  So the circuit for the RAM is very
simple (figure 5).

This is designed such that the 2 KByte sits in the bottom 2 Kwords of podule
space, and the top 2 Kwords are free for other hardware on our podule.  This is an often
used configuration, as the address decoding is quite simple and the RAM (or
more commonly flash or EPROM) is in the right place for the Expansion Card
ID, which we'll discuss next time.

Before we finish, we ought to check the timing to ensure our data is going to
come out all right.  At its fastest the cycle time is 375ns as we have
discussed.  Picking a 6116 out of my junk box, I see its access time is
150ns (as it's written on the top), so that chip should be fine.  As it
happens, 375ns is enough that any chip made since the 1970s should able to
handle it.

If you make this circuit, with the RAM in place you may find your computer
occasionally fails to start up or aborts when you switch it on.  This is the
reason I suggested you keep bit 7 high last time - and in fact it's working perfectly correctly.  I'll talk about this next time when we enter the world of
EcIDs and podule ROMs.
