MODULE busif

TITLE 'Bus interface for A4 ethernet card'
" version 20030328
" by Theo Markettos (theo@markettos.org.uk)
" under open hardware licence

"CPLD DEVICE 'ispLSI2032EJ'

Declarations

" input pins
!S2, !S4, LA2, LA3, LA4, LA5 pin 26, 22, 28, 17, 16, 15;
!WBE, CLK2, CLK2I, !PRE, !PWE pin 27, 11, 31, 18, 19;
ETHIRQ, !ECON pin 4, 25;
D0, D1 pin 42, 41;
!RST pin 14;
"CLK2I is externally connected to CLK2, and allows use of the clock
"  in product terms for testing

" output pins
!OE245, CPAB, DIR245, DIR646, CPBA, !OE646 pin 9, 8, 10, 7, 6, 5 istype 'com';
!IOR, !IOW, RESET, !SLEEP pin 44, 43, 40, 39 istype 'com';
!AEN pin 3 istype 'com';
PIRQ, EFIQ pin 21, 20 istype 'com';

EQUATIONS

AEN = S2 & LA2;
DIR245 = WBE;
OE245 = S2 & ECON;
IOR = (PRE & ECON);
IOW = (PWE & ECON);
SLEEP = ECON;
"DIR646 = PWE;
DIR646 = WBE;
OE646 = S2 & ((!LA2 & PRE) # (LA2 & PWE)) & ECON;
CPAB = !(PWE & S2 & !LA2) & ECON;
CPBA = !(PRE & S2 & LA2) & ECON;
"OE646 = 1;
"CPAB = !(PWE & S2);
"CPBA = !(PRE & S2);
"CPAB = CLK2I;

PIRQ = 0;
PIRQ.oe = ETHIRQ;

EFIQ = 1;
EFIQ.oe = 0;

RESET = RST;

END