PERQ3 CPU Technical Description ------------------------------- CPU section ----------- Main CPU is the 68020 (U43). Data bus is buffered by '245s (U37,U36,U29,U28), which are enabled on a CPU cycle not involving the FPU (via U93d). Clocks from memory board buffered/distributed by 74ALS804 (U64). Bus control lines buffered by U71 ('245). 68881 FPU is connected in the standard way, apart from CS*. FPU has its own clock U30. '138 decoder (U83) decodes CPU address during a CPU space cycle (detected by '10 NAND gate U76b), and provides interrupt acknowledge and FPU chip select signals. FPU Enable signal from MSR1 can disable FPU chip select via OR gate U115c. Power control and Reset ----------------------- Pressing boot switch on monitor clears power control flip-flop (U31b) and energises solid-state relay via U22c ('132 NAND gate) and connector ZK1. CPU DS signal clocks Power Off signal (from MSR0) intro U31b, allowing the CPU to turn the machine off. RTCStby signal from MSR1 is clocked into U31a by DS, and provides Standby signal for real time clock chip. The chips used in the power control circuit are powered from the 3V battery via the usual pair of diodes. ACLO* signal from PSU is delayed by U13b ('123) and then combined with the similarly delayed program reset signal from MSR0 by O/C AND gate U18a ('11). Resulting main machine Rst* signal is also capable of being pulled low by PSU DCLO* via a diode. I/O Address decoder ------------------- PALs U137, U144, U151, U158 decode CPU address, Write Enable signal, and Access Enable* to provide chip select signals for the on-board I/O devices. Module 0 I/O - machine status registers, etc -------------------------------------------- Top 8 CPU data bus lines (used for byte cycles) are buffered by '245 (U46) to provide an 8-bit peripheral data bus. MSR 0 consists of 2 '175 4-bit flip-flops (U51 and U41), and can be read back via '244 buffer U47. Similarly MSR1 consists of U56 and U85 ('175), rad back through U50. DIP switch pack at U55 is buffered onto the 8 bit bus via U49 ('244), while CPU board ID PROM U45 (82S123) directly drives this bus. All these devices are enabled by the address decoder. Onboard memory -------------- PAL U130 (16L8), together with PAL U144 (part of the address decoder) and U76b ('08 AND gate) form the memory address decoder, which provide enable signals to the boot ROM U92 (27256) and 8K test RAM (U108, 6264) MMU pager --------- Pager relocation table consists of 84H16 16K RAM hybrids. 16K*20 RAM (U95, U111, U125, U139,U140) stores relocation address and protection flags, while 16K*32 RAM (U96, U104, U112, U118, U133, U103, U117, U132) stores next table address, tag bits, and pager control flags. Address lines to approximately half the RAMs are buffered by U154 and U153 ('244). Top 22 lines of CPU address are extended by 8 bits from the ASI (Address Space Identifier) registers and then split into a 14 bit table address and a 16 bit tag address (split is selected in part by the jumper plug at U155) . Initially 14 bit table address is applied to the relocation RAM address lines via buffers U127 and U148 ('245). Tag address bits are compared with the tag address stored in the RAM by '521 comparators U149 and U142. Header bit is checked by U89b ('86), along with U129b ('74 flipflop) to ensure this is the first entry of a chain. Access mode is checked by '64 AOI gate U128 and its related logic. These signals are all combined by '64 AOI gate U135 to produce a Page Found signal. If the page is not found, then the next table address from the RAMs is latched in the pager address PALs U105, U113, U119, U134, U141 (16R4's). These are then enabled by flip-flop U60a ('74), and the cycle repeated using state control latch U59a and associated logic. Flip-flop U129b is now set, so that all subsequent entries must have the header bit clear. This cycle continues until either the correct entry is found, or the search wraps around to an entry with the header bit set. In the latter case, latch U59c ('175) and O/C AND gate U18b ('11) generate a bus error. Address output from the table is buffered by U136 and U143 ('245s) and drives the main CPU address bus. Pager can be bypassed by buffers U150 and U157 ('245s) which gate the CPU address lines onto the system address bus. This is controlled by part of the pager control PAL U106 (16L8) which combines the CPU FC signals with the bypass signals from MSR0. The CPU can read/write the pager RAMs via address multiplexers/buffers (in the pager address PALs) and data buffers U94, U124, U131, U86, U110, U102, U116). This is controlled by the PAL U106. Pager status lines are read on the top 8 bits of the flag RAM via buffer U15 ('244). Any access to memory via the pager is detected by usage control PAL U147 (16R4), and thus recorded in the usage RAM U146 (84H16), which is addressed by the pager address output. The CPU can read/write this RAM via the PAL also. Address Space Identifiers ------------------------- The top 8 bits of the virtual address are provided by a pair of '374 registers which store the ASI value for user (U78) and supervisor (U84) accesses. They can be read back via the '244 buffer at U72. Gates U98d ('02) and U66d ('32), together with U79c ('08) select the correct ASI register to read or feed to the pager. Simple Bus Cycle ---------------- U81 ('374) and it's associated logic delays the AS signal from the CPU and provides DSACK signals for accesses to the non-68000 peripherals and the pager RAMs. DMA and bus arbitration ----------------------- Bus arbiter U58 (68452) handles requests from the Raster Op processor (level 1), DMA (level 3) and Network (level 5) and provides the appropriate grant signals. The 68450 DMA device (U53) provides a DMA channel for the SCSI chip. The muliplexed address and data bus of this device is separated by Address latches U62 and U63 ('373) and data buffers U35 and U34 ('245). Priority encoder U74 ('148) encodes the Bus Error, Reset and control signals into the BEC signals needed by the 68450. Latch U67 ('374), buffer U80 a,b,c ('125) and associated logic converts the 68000-like control signals of the 68450 into the 68020-like ones used in the rest of the system. Interrupts ---------- Interrupt requests from the various peripherals are encoded onto the CPU IPL lines by the 16L8 PAL at U77. The system address is decoded during an interrupt acknowledge cycle by U91 ('138) to provide acknowledge signals to those devices that require them, while SR flip-flop U99c,d ('00) provides priority arbitration between the DMA controller and SCSI port. SCSI ---- The NCR 5380 at location U123, forms a standard SCSI port, terminated by RP6 and RP7. The SCSI bus leaves the CPU board on ZE1, and is linked to the disk controller. DDS and machine ID ------------------ Data for the diagnostic display is latched in U132 ('374) and routed to the DDS connector ZU2. This data consists of 4 enable signals that select one of the display digits (1 out of 4 code) and 4 bits of digit data. The low 5 machine address lines, together with the Machine ID enable signal are buffered by U138 ('245) and fed to the ID PROM on the DDS board. Data from this PROM is buffered by U145 ('245) and fed to the 8-bit data bus. Real Time Clock --------------- State latch U75 ('374) and associated logic provides the timing/control signals for the real time clock chip and the DSACK0 signal for real time clock and serial port bus cycles. System address bus is buffered by U38 ('244) and sent to the real time clock. Real time clock data is latched in the bidirectional latch U39 (2952) and transfered to/from the 8 bit data bus. The real time clock is U5 (146818A). It is clocked by a 32768Hz crystal in conjuction with NAND gate U15d (4093). The real time clock chip and the oscillator are battery-backed by the 3V battery used for the power switch. Serial ports ------------ The bus cycles for the serial port chips are produced by the same logic used for the real time clock. U16 (Z8350) is the main serial chip, and is connected to the system bus in the standard way. The port lines are buffered by 1488s and 1489s (U1-U3 and U6-U9) and connected to the RS232 connectors (ZD1, ZD2) on the real panel. Auxilliary handshake outputs are provided by U23 ('174) which are similarly buffered by sections of the 1488s. Auxilliary handshake inputs are converted to TTL levels by sections of the 1489s and then latched by U24 ('374) and fed to the system data bus. U17 is the tablet/keyboard/sound serial chip. Port B is used for the tablet, and the output lines are fed to the multiplexer PCB in the monitor via the memory board and video cable. The input lines are produced by the video head interface. Port A TxD provides the sound output, and is similarly routed to the monitor, while the keyboard data input from the video head interface drives the RxD line of port A of U17. Video head interface and mouse port ----------------------------------- Inputs from the keyboard, tablet, mouse and optional speech system are combined into a serial bit stream by logic in the monitor base. This bitstream is reconverted to parallel bits by the shift registers U14 and U4 ('595). Counter U11 ('191) and latch U21 ('175) provide the clock and sync signals for this bitstream. The resulting keyboard and tablet signals are connected to U17 in the serial port section. The mouse lines are latched by U61 ('373) (to prevent them changing while being read) and fed to the comparator U48 (2150) which contains a latch that stores the current mouse state. When they change, U48 provides a mouse interrupt. Reading the mouse port updates the value held in U48 via OR gate U57b ('32), and removes the interrupt. The mouse lines can be read onto the 8 bit data bus via U65 ('245). The speech control line, S4, is connected to the EXT connector on the CPU board, and is thus passed to the expansion cabinet. Ethernet -------- U42 (82586) is the main ethernet controller device. This chip contains its own DMA controller, and the multiplexed address/data bus is separated by data buffers U26 and U27 ('245s) and address latches U68, U70 and U69 ('373s). The bus state signals from U42 are decoded by U52 (8288) to provide Write enable and address and data control signals. Since the 82586 has an Intel compatible bus structure, PAL U25 (16R6) and the associated logic is used to provide 68020-compatable address and data strobes when the 82586 is performing DMA operations. U54 ('244) provides suitable bus control lines during ethernet DMA cycles to ensure that 16 bit transfers occur, and that the pager is bypassed. Manchester encoder/decoder U10 (8023A) interfaces the 82586 to the AUI port ZC1 on the rear of the system. Graphics Processor ------------------ The graphics processor consists of a pair of 29116 ALUs, one to calculate system addresses and the other to perform data manipulations, together with the associated bus buffers, a 16 bit bidirectional register to transfer data between the 2 ALUs, a 4K*64 bit control store, sequencer logic and associated instruction decoders and control circuits. PROMs U238 and U237 (27S291) and latches U235 and U239 form a state machine that controls the graphics processor bus cycle. Inputs to this state machine come from the raster op bus control logic (latched in some sections of U217 ('374) and the system bus, and are combined by multiplexer U219 ('157), which is controlled by the state machine. The outputs of this multiplexer are connected to the address inputs of the state machine PROMs. PAL U236 (16R4) decodes the state machine latch and system bus signals and provides control store adress control signals. PAL U218 (16R4) similarly provides control store enables and data buffer control signals. The CPU address lines are transfered to the control store address bus via budffers U213 and U192 ('244s) and the data bus is buffered by U161 - U168 ('245s). PAL U197 (16H8) and the associated logic is driven by outputs from the bus cycle state machine, along with system bus signals, and provides the necessary bus request and acknowledge signals for both control store accesses and graphics processor DMA cycles. The bus control signals from the control PALs and state machine are buffered by U175 ('245) and connected to the system bus. The control store is logically 4K 64 bit words, and consists of 16 81C68 RAMs at locations U183-U190 and U204-U211. The outputs of the control store are used to control the rest of the graphics processor. The control store is sequenced by a 12 bit counter consisting of 3 '569 devices (U191,U212,U232). These can be parallel loaded (for jump operations) from either the top 12 bits of the microcode word (bits 52-63) or from the bottom 12 bits of the data ALU output, selected by bit 47 of the microcode word using multiplexers U203, U227 and U228 ('157). The jump condition is selected by the '251 multiplexers U230 and U241, controlled by bits 48-51 of the microcode word. The sequencer clock is produced by the shift register U181 ('194) and its associated logic, while AOI gate U215 ('64) provides wait state logic to hold the clock during system bus cycles. Microcode bit 41 is latched by U242b ('175) to provide a bus request signal, and bits 43-46 are latched by U231 and U201 ('174) to provide transfer size and FC bus control signals. All of bits 41-45 are decoded by PAL U243 (16R6) to produce processor control signals, while bit 40 is latched by U242a to produce the address ALU bus select signal. The lowest 16 microcode data bits (0-15) provide the instruction word for the data ALU U159 (29116). The lowest 2 are combined with the I register bit 9 by PAL U233 (16R4) (controlled by data bit 32) and latched in U240 ('374) while the next 8 ALU control signals either come from the I register or microcode data bits 5-12, selected by multiplexers U229 and U223 ('399s), selected by microcode data bits 33 and 34. This allows the Data ALU instruction to be modified under microprogram control. The data outputs of the data ALU can be latched in the I register U202 (29281) for this purpose. U171 and U172 (29F52s) provide a 16 bit bidirectional transfer register between the address and data ALUs, while the data ALU bus can also be transfered to/from the system data bus via the buffers U170, U169, U160, U182 (29F52s). The data ALU bus buffers are controlled by PAL U224 (16R6) which decodes microcode bits 35-39 and also I register bit 8. The address ALU is U214 (29116), the instruction for which is latched in U226 and U234 ('374) from bits 16-31 of the microcode word. The data bus of this ALU is connected to the tranfer register and can be latched in the buffers U180, U179 (29520) and U177, U178 ('374) which drive the system address bus. The lowest 3 bits are also latched in U176 (29520) which provides the FC signals during graphics processor DMA cycles.