x86-model: New program, prints CPUID information.

[misc] / x86-model.1

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+.TH x86-model 1 "30 April 2009" "Edgeware tools"
+.SH NAME
+x86-model \- show x86 CPU model information and (a bit) more
+.SH SYNOPSIS
+.B x86-model
+.RB [ \-v ]
+.RB [ \-i \c
+.RB | \-d \c
+.RB |[ \-s ]
+.IR leaf ] \c
+.RB | \-x
+.IR leaf ]
+.SH DESCRIPTION
+The
+.b x86-model
+program shows basic information about the host's x86-based processor,
+gleaned from the CPUID instruction.  It doesn't work on other processors
+at all.  The
+.B \-v
+flag causes more detailed information to be output.
+.PP
+The CPUID instruction reads an index in the EAX register which selects a
+`leaf' of information; it sets the output registers EAX, EBX, ECX, and
+EDX, to the appropriate values for the selected leaf.
+.PP
+By default, or with
+.BR \-i ,
+it shows the `display family' and `display model' information for the
+processor, in the form
+.IB family _ model H
+which is used in the tables in Appendix C of Intel's optimization
+guide.  In verbose mode, the processor type, family, model and stepping
+are shown separately.
+.PP
+With the
+.B \-d
+option, all of the available CPUID information is dumped to standard
+output.  Each line has the form
+.IP
+.IB leaf :
+.I eax
+.I ebx
+.I ecx
+.I edx
+.PP
+Verbose mode makes no difference.
+.PP
+With the
+.B \-s
+option (or just a
+.I leaf
+index), prints the leaf of information selected by
+.IR leaf ,
+as four hexadecimal numbers separated by spaces.  In verbose mode, the
+output is written on four lines, labelled with the appropriate register
+names.
+.PP
+With the
+.B \-x
+option, the behaviour is as for
+.B \-s
+except that `extended function' information is selected by toggling bit
+31 of the leaf index.
+.PP
+If no option is given, but there is a command-line argument, then the
+behaviour is as for
+.B \-s
+with the leaf taken from the argument; otherwise the behaviour is as for
+.BR \-i .
+.SH SEE ALSO
+.BR cpuid (1).
+.PP
+.I "Intel 64 and IA-32 Architectures Software Developer's Manual"
+.br
+.I "Intel 64 and IA-32 Architectures Optimization Reference Manual"