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mtimeout.c: Add `--kill-after' and `--no-kill' options.
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1.TH x86-model 1 "30 April 2009" "Edgeware tools"
2.SH NAME
3x86-model \- show x86 CPU model information and (a bit) more
4.SH SYNOPSIS
5.B x86-model
6.RB [ \-v ]
7.RB [ \-i \c
8.RB | \-d \c
9.RB |[ \-s ]
10.IR leaf ] \c
11.RB | \-x
12.IR leaf ]
13.SH DESCRIPTION
14The
15.b x86-model
16program shows basic information about the host's x86-based processor,
17gleaned from the CPUID instruction. It doesn't work on other processors
18at all. The
19.B \-v
20flag causes more detailed information to be output.
21.PP
22The CPUID instruction reads an index in the EAX register which selects a
23`leaf' of information; it sets the output registers EAX, EBX, ECX, and
24EDX, to the appropriate values for the selected leaf.
25.PP
26By default, or with
27.BR \-i ,
28it shows the `display family' and `display model' information for the
29processor, in the form
30.IB family _ model H
31which is used in the tables in Appendix C of Intel's optimization
32guide. In verbose mode, the processor type, family, model and stepping
33are shown separately.
34.PP
35With the
36.B \-d
37option, all of the available CPUID information is dumped to standard
38output. Each line has the form
39.IP
40.IB leaf :
41.I eax
42.I ebx
43.I ecx
44.I edx
45.PP
46Verbose mode makes no difference.
47.PP
48With the
49.B \-s
50option (or just a
51.I leaf
52index), prints the leaf of information selected by
53.IR leaf ,
54as four hexadecimal numbers separated by spaces. In verbose mode, the
55output is written on four lines, labelled with the appropriate register
56names.
57.PP
58With the
59.B \-x
60option, the behaviour is as for
61.B \-s
62except that `extended function' information is selected by toggling bit
6331 of the leaf index.
64.PP
65If no option is given, but there is a command-line argument, then the
66behaviour is as for
67.B \-s
68with the leaf taken from the argument; otherwise the behaviour is as for
69.BR \-i .
70.SH SEE ALSO
71.BR cpuid (1).
72.PP
73.I "Intel 64 and IA-32 Architectures Software Developer's Manual"
74.br
75.I "Intel 64 and IA-32 Architectures Optimization Reference Manual"