From: Mark Wooding Date: Mon, 7 Nov 2016 12:24:35 +0000 (+0000) Subject: symm/salsa20-arm-neon.S: Improve output permutation still further. X-Git-Tag: 2.3.0~15 X-Git-Url: http://www.chiark.greenend.org.uk/ucgi/~mdw/git/catacomb/commitdiff_plain/f48fb6a6b1e0f29a45b42beae638ef9886312579 symm/salsa20-arm-neon.S: Improve output permutation still further. --- diff --git a/symm/salsa20-arm-neon.S b/symm/salsa20-arm-neon.S index 9d553d3a..cea40192 100644 --- a/symm/salsa20-arm-neon.S +++ b/symm/salsa20-arm-neon.S @@ -205,33 +205,28 @@ FUNC(salsa20_core_arm_neon) b 0b - // Almost there. Firstly the feedfoward addition. + // Almost there. Firstly the feedfoward addition. Also, establish a + // constant which will be useful later. 9: vadd.u32 q0, q8, q12 // 0, 5, 10, 15 - vadd.u32 q9, q9, q13 // 4, 9, 14, 3 - vadd.u32 q10, q10, q14 // 8, 13, 2, 7 - vadd.u32 q11, q11, q15 // 12, 1, 6, 11 + vmov.i64 q12, #0xffffffff // = (-1, 0, -1, 0) + vadd.u32 q1, q9, q13 // 4, 9, 14, 3 + vadd.u32 q2, q10, q14 // 8, 13, 2, 7 + vadd.u32 q3, q11, q15 // 12, 1, 6, 11 // Next we must undo the permutation which was already applied to the - // input. This can be done juggling values in registers, with the - // following fancy footwork: some row rotations, a transpose, and - // some more rotations. - vext.32 q9, q9, q9, #3 // 3, 4, 9, 14 - vext.32 q10, q10, q10, #2 // 2, 7, 8, 13 - vext.32 q11, q11, q11, #1 // 1, 6, 11, 12 - - vzip.32 q0, q10 // 0, 2, 5, 7 - // 10, 8, 15, 13 - vzip.32 q11, q9 // 1, 3, 6, 4 - // 11, 9, 12, 14 - - vzip.32 q0, q11 // 0, 1, 2, 3 - // 5, 6, 7, 4 - vzip.32 q10, q9 // 10, 11, 8, 9 - // 15, 12, 13, 14 - - vext.32 q1, q11, q11, #3 // 4, 5, 6, 7 - vext.32 q2, q10, q10, #2 // 8, 9, 10, 11 - vext.32 q3, q9, q9, #1 // 12, 13, 14, 15 + // input. The core trick is from Dan Bernstein's `armneon3' + // implementation, but with a lot of liposuction. + vmov q15, q0 + + // Sort out the columns by pairs. + vbif q0, q3, q12 // 0, 1, 10, 11 + vbif q3, q2, q12 // 12, 13, 6, 7 + vbif q2, q1, q12 // 8, 9, 2, 3 + vbif q1, q15, q12 // 4, 5, 14, 15 + + // Now fix up the remaining discrepancies. + vswp D1(q0), D1(q2) + vswp D1(q1), D1(q3) // And with that, we're done. vstmia r2, {QQ(q0, q3)}