chiark / gitweb /
ian [Thu, 2 Sep 2004 02:06:44 +0000 (02:06 +0000)]
before fix up fet pins
ian [Thu, 2 Sep 2004 01:47:34 +0000 (01:47 +0000)]
silk for point numbering
ian [Thu, 2 Sep 2004 01:39:47 +0000 (01:39 +0000)]
trimmed again
ian [Thu, 2 Sep 2004 01:39:33 +0000 (01:39 +0000)]
larger header-20
ian [Thu, 2 Sep 2004 01:30:24 +0000 (01:30 +0000)]
bus connector and annotations
ian [Thu, 2 Sep 2004 01:23:20 +0000 (01:23 +0000)]
detectors routes
ian [Thu, 2 Sep 2004 01:21:30 +0000 (01:21 +0000)]
before reshrink
ian [Thu, 2 Sep 2004 01:20:21 +0000 (01:20 +0000)]
new BUS connector
ian [Thu, 2 Sep 2004 01:03:56 +0000 (01:03 +0000)]
mounting hole diagrams
ian [Thu, 2 Sep 2004 00:38:00 +0000 (00:38 +0000)]
routes again
ian [Thu, 2 Sep 2004 00:10:57 +0000 (00:10 +0000)]
truncate points plug and trim layout by 25th
ian [Thu, 2 Sep 2004 00:08:03 +0000 (00:08 +0000)]
swap plug and socket
ian [Wed, 1 Sep 2004 23:56:14 +0000 (23:56 +0000)]
connector INDIV0 diagram
ian [Wed, 1 Sep 2004 23:56:02 +0000 (23:56 +0000)]
ignore gerber outputs
ian [Wed, 1 Sep 2004 23:35:47 +0000 (23:35 +0000)]
delete offboard silk from indiv0
ian [Wed, 1 Sep 2004 23:32:23 +0000 (23:32 +0000)]
before adjust silk
ian [Mon, 30 Aug 2004 02:45:26 +0000 (02:45 +0000)]
proper creation of oprints-l
ian [Mon, 30 Aug 2004 02:40:36 +0000 (02:40 +0000)]
pcboprints makes oprints-l
ian [Mon, 30 Aug 2004 02:40:05 +0000 (02:40 +0000)]
do not clean pcb output postscript files
ian [Mon, 30 Aug 2004 02:35:25 +0000 (02:35 +0000)]
now all a4
ian [Mon, 30 Aug 2004 02:16:47 +0000 (02:16 +0000)]
a3 handling improved
ian [Mon, 30 Aug 2004 01:49:42 +0000 (01:49 +0000)]
smaller; passes nicely; is next draft
ian [Mon, 30 Aug 2004 01:47:29 +0000 (01:47 +0000)]
fixes, routes nicely, before shrink manually again
ian [Mon, 30 Aug 2004 01:47:15 +0000 (01:47 +0000)]
sense8!
ian [Mon, 30 Aug 2004 00:11:29 +0000 (00:11 +0000)]
nicer printing arrangements
ian [Sun, 29 Aug 2004 20:20:55 +0000 (20:20 +0000)]
detectors draft finished
ian [Sun, 29 Aug 2004 20:05:54 +0000 (20:05 +0000)]
before resize
ian [Sun, 29 Aug 2004 20:00:22 +0000 (20:00 +0000)]
before shift
ian [Sun, 29 Aug 2004 19:56:50 +0000 (19:56 +0000)]
working on routing
ian [Sun, 29 Aug 2004 19:41:00 +0000 (19:41 +0000)]
really routes but still no room for text
ian [Sun, 29 Aug 2004 19:36:53 +0000 (19:36 +0000)]
routes but text does not fit
ian [Sun, 29 Aug 2004 18:50:24 +0000 (18:50 +0000)]
before much manual routing
ian [Sun, 29 Aug 2004 18:20:46 +0000 (18:20 +0000)]
reversers draft finished
ian [Sun, 29 Aug 2004 18:18:35 +0000 (18:18 +0000)]
before shrink
ian [Sun, 29 Aug 2004 17:30:31 +0000 (17:30 +0000)]
mounting holes placed
ian [Sun, 29 Aug 2004 16:29:25 +0000 (16:29 +0000)]
print detectors too
ian [Sun, 29 Aug 2004 16:29:17 +0000 (16:29 +0000)]
mounting holes
ian [Sun, 29 Aug 2004 00:22:26 +0000 (00:22 +0000)]
working on routing
ian [Sun, 29 Aug 2004 00:15:37 +0000 (00:15 +0000)]
ground and power routing
ian [Sat, 28 Aug 2004 23:37:34 +0000 (23:37 +0000)]
pic senses done? wip
ian [Sat, 28 Aug 2004 22:49:58 +0000 (22:49 +0000)]
sense lines route wip
ian [Sat, 28 Aug 2004 19:28:41 +0000 (19:28 +0000)]
rats nicely laid out etc except for pic pins
ian [Sat, 28 Aug 2004 18:30:53 +0000 (18:30 +0000)]
before reorg sense
ian [Sat, 28 Aug 2004 18:09:50 +0000 (18:09 +0000)]
redo layout placement wip
ian [Sat, 28 Aug 2004 17:50:31 +0000 (17:50 +0000)]
before delete stuff for redo
ian [Sat, 28 Aug 2004 17:30:30 +0000 (17:30 +0000)]
before move some rs*
ian [Sat, 28 Aug 2004 16:56:44 +0000 (16:56 +0000)]
rasN
ian [Sat, 28 Aug 2004 16:41:06 +0000 (16:41 +0000)]
make more like detectors. wip. problem with netlist
ian [Sat, 28 Aug 2004 16:26:43 +0000 (16:26 +0000)]
before c&p oc
ian [Sat, 28 Aug 2004 16:25:43 +0000 (16:25 +0000)]
before c&p oc
ian [Sat, 28 Aug 2004 16:04:06 +0000 (16:04 +0000)]
before turn brs
ian [Sat, 28 Aug 2004 15:27:40 +0000 (15:27 +0000)]
rectifiers
ian [Thu, 26 Aug 2004 18:58:54 +0000 (18:58 +0000)]
rename
ian [Thu, 26 Aug 2004 18:57:55 +0000 (18:57 +0000)]
generates detectors as well as reversers netlist
ian [Thu, 26 Aug 2004 18:57:51 +0000 (18:57 +0000)]
clone and hack
ian [Thu, 26 Aug 2004 02:59:11 +0000 (02:59 +0000)]
fit fab
ian [Thu, 26 Aug 2004 02:54:22 +0000 (02:54 +0000)]
Makefile in oprint target; fit fab on
ian [Thu, 26 Aug 2004 02:49:26 +0000 (02:49 +0000)]
more printing
ian [Thu, 26 Aug 2004 02:11:41 +0000 (02:11 +0000)]
autoroutes again
ian [Thu, 26 Aug 2004 02:01:11 +0000 (02:01 +0000)]
straighten silk texts
ian [Thu, 26 Aug 2004 01:50:23 +0000 (01:50 +0000)]
layer id texts
ian [Thu, 26 Aug 2004 01:40:31 +0000 (01:40 +0000)]
swap bus <-> indiv1
ian [Thu, 26 Aug 2004 01:35:36 +0000 (01:35 +0000)]
ptd vertical mount
ian [Thu, 26 Aug 2004 01:05:16 +0000 (01:05 +0000)]
indiv0-2 to indiv1-2 thick
ian [Thu, 26 Aug 2004 01:02:58 +0000 (01:02 +0000)]
pc <-> pd
ian [Thu, 26 Aug 2004 00:57:12 +0000 (00:57 +0000)]
pad/pin sizes
ian [Thu, 26 Aug 2004 00:14:02 +0000 (00:14 +0000)]
print => oprint for better completion
ian [Wed, 25 Aug 2004 01:28:37 +0000 (01:28 +0000)]
how to view .print-*.ps
ian [Wed, 25 Aug 2004 01:27:26 +0000 (01:27 +0000)]
print front back and assembly
ian [Wed, 25 Aug 2004 01:22:18 +0000 (01:22 +0000)]
retile to fit on A4
ian [Wed, 25 Aug 2004 01:04:11 +0000 (01:04 +0000)]
rerun with only selected sides
ian [Wed, 25 Aug 2004 01:01:18 +0000 (01:01 +0000)]
drc errors ok even when rerouting; resave ?
ian [Wed, 25 Aug 2004 00:59:01 +0000 (00:59 +0000)]
drc errors ok even when rerouting
ian [Wed, 25 Aug 2004 00:56:46 +0000 (00:56 +0000)]
manual fixup of drc errors
ian [Wed, 25 Aug 2004 00:49:33 +0000 (00:49 +0000)]
with drc errors and rcs id
ian [Wed, 25 Aug 2004 00:42:03 +0000 (00:42 +0000)]
autorouter makes drc errors
ian [Wed, 25 Aug 2004 00:13:10 +0000 (00:13 +0000)]
before change d25 again
ian [Tue, 24 Aug 2004 23:48:54 +0000 (23:48 +0000)]
helping autorouter
ian [Tue, 24 Aug 2004 22:46:11 +0000 (22:46 +0000)]
before reorg d and manual stuff and...
ian [Tue, 24 Aug 2004 22:34:36 +0000 (22:34 +0000)]
placement work, mounting gaps
ian [Tue, 24 Aug 2004 20:14:10 +0000 (20:14 +0000)]
points connector varied
ian [Tue, 24 Aug 2004 20:13:39 +0000 (20:13 +0000)]
allow : stuff things : syntax
ian [Tue, 24 Aug 2004 19:57:04 +0000 (19:57 +0000)]
generate same netlist but split data from code
ian [Tue, 24 Aug 2004 19:28:15 +0000 (19:28 +0000)]
fancier netlist generation
ian [Mon, 23 Aug 2004 03:57:56 +0000 (03:57 +0000)]
wip nice
ian [Mon, 23 Aug 2004 03:28:08 +0000 (03:28 +0000)]
furtling seems ok
ian [Mon, 23 Aug 2004 03:16:07 +0000 (03:16 +0000)]
after fiddle manually
ian [Mon, 23 Aug 2004 03:14:30 +0000 (03:14 +0000)]
before fiddle manually
ian [Mon, 23 Aug 2004 02:15:59 +0000 (02:15 +0000)]
points
ian [Mon, 23 Aug 2004 00:35:08 +0000 (00:35 +0000)]
much manual gnd/vcc routing
ian [Sun, 22 Aug 2004 23:25:17 +0000 (23:25 +0000)]
pdw circuitry. need manual reverse0..5 routing
ian [Sun, 22 Aug 2004 22:42:40 +0000 (22:42 +0000)]
wip routes
ian [Sun, 22 Aug 2004 22:27:15 +0000 (22:27 +0000)]
largely routes
ian [Sun, 22 Aug 2004 21:25:53 +0000 (21:25 +0000)]
netlist loads ok but still everything wip
ian [Sun, 22 Aug 2004 18:13:45 +0000 (18:13 +0000)]
reversers pcb and netlist wip - netlist still broken
ian [Sun, 22 Aug 2004 01:29:33 +0000 (01:29 +0000)]
some shuffling - wip
ian [Sun, 22 Aug 2004 01:25:58 +0000 (01:25 +0000)]
has term0 connector
ian [Sat, 21 Aug 2004 17:54:19 +0000 (17:54 +0000)]
reversers new connector wip
ian [Sat, 21 Aug 2004 15:36:59 +0000 (15:36 +0000)]
turn real wip
ian [Sat, 21 Aug 2004 15:20:09 +0000 (15:20 +0000)]
turn real wip
~ijackson / trains.git / log