chiark / gitweb /
ian [Wed, 25 Aug 2004 01:27:26 +0000 (01:27 +0000)]
print front back and assembly
ian [Wed, 25 Aug 2004 01:22:18 +0000 (01:22 +0000)]
retile to fit on A4
ian [Wed, 25 Aug 2004 01:04:11 +0000 (01:04 +0000)]
rerun with only selected sides
ian [Wed, 25 Aug 2004 01:01:18 +0000 (01:01 +0000)]
drc errors ok even when rerouting; resave ?
ian [Wed, 25 Aug 2004 00:59:01 +0000 (00:59 +0000)]
drc errors ok even when rerouting
ian [Wed, 25 Aug 2004 00:56:46 +0000 (00:56 +0000)]
manual fixup of drc errors
ian [Wed, 25 Aug 2004 00:49:33 +0000 (00:49 +0000)]
with drc errors and rcs id
ian [Wed, 25 Aug 2004 00:42:03 +0000 (00:42 +0000)]
autorouter makes drc errors
ian [Wed, 25 Aug 2004 00:13:10 +0000 (00:13 +0000)]
before change d25 again
ian [Tue, 24 Aug 2004 23:48:54 +0000 (23:48 +0000)]
helping autorouter
ian [Tue, 24 Aug 2004 22:46:11 +0000 (22:46 +0000)]
before reorg d and manual stuff and...
ian [Tue, 24 Aug 2004 22:34:36 +0000 (22:34 +0000)]
placement work, mounting gaps
ian [Tue, 24 Aug 2004 20:14:10 +0000 (20:14 +0000)]
points connector varied
ian [Tue, 24 Aug 2004 20:13:39 +0000 (20:13 +0000)]
allow : stuff things : syntax
ian [Tue, 24 Aug 2004 19:57:04 +0000 (19:57 +0000)]
generate same netlist but split data from code
ian [Tue, 24 Aug 2004 19:28:15 +0000 (19:28 +0000)]
fancier netlist generation
ian [Mon, 23 Aug 2004 03:57:56 +0000 (03:57 +0000)]
wip nice
ian [Mon, 23 Aug 2004 03:28:08 +0000 (03:28 +0000)]
furtling seems ok
ian [Mon, 23 Aug 2004 03:16:07 +0000 (03:16 +0000)]
after fiddle manually
ian [Mon, 23 Aug 2004 03:14:30 +0000 (03:14 +0000)]
before fiddle manually
ian [Mon, 23 Aug 2004 02:15:59 +0000 (02:15 +0000)]
points
ian [Mon, 23 Aug 2004 00:35:08 +0000 (00:35 +0000)]
much manual gnd/vcc routing
ian [Sun, 22 Aug 2004 23:25:17 +0000 (23:25 +0000)]
pdw circuitry. need manual reverse0..5 routing
ian [Sun, 22 Aug 2004 22:42:40 +0000 (22:42 +0000)]
wip routes
ian [Sun, 22 Aug 2004 22:27:15 +0000 (22:27 +0000)]
largely routes
ian [Sun, 22 Aug 2004 21:25:53 +0000 (21:25 +0000)]
netlist loads ok but still everything wip
ian [Sun, 22 Aug 2004 18:13:45 +0000 (18:13 +0000)]
reversers pcb and netlist wip - netlist still broken
ian [Sun, 22 Aug 2004 01:29:33 +0000 (01:29 +0000)]
some shuffling - wip
ian [Sun, 22 Aug 2004 01:25:58 +0000 (01:25 +0000)]
has term0 connector
ian [Sat, 21 Aug 2004 17:54:19 +0000 (17:54 +0000)]
reversers new connector wip
ian [Sat, 21 Aug 2004 15:36:59 +0000 (15:36 +0000)]
turn real wip
ian [Sat, 21 Aug 2004 15:20:09 +0000 (15:20 +0000)]
turn real wip
ian [Sat, 21 Aug 2004 14:22:07 +0000 (14:22 +0000)]
ignore reversers pcb stuff
ian [Sat, 21 Aug 2004 14:21:03 +0000 (14:21 +0000)]
delete abortive pic element
ian [Sat, 21 Aug 2004 14:20:50 +0000 (14:20 +0000)]
abortive pic element
ian [Fri, 20 Aug 2004 16:44:56 +0000 (16:44 +0000)]
swap in and out for DEFG
ian [Fri, 20 Aug 2004 01:17:30 +0000 (01:17 +0000)]
debugged. oc still weird
ian [Fri, 20 Aug 2004 00:36:55 +0000 (00:36 +0000)]
flash-all really does flash RD7
ian [Fri, 20 Aug 2004 00:34:33 +0000 (00:34 +0000)]
flash-all actually flashes RD7 too
ian [Fri, 20 Aug 2004 00:28:58 +0000 (00:28 +0000)]
bugfixes
ian [Sat, 14 Aug 2004 11:54:52 +0000 (11:54 +0000)]
i/o copying ?
ian [Thu, 12 Aug 2004 19:17:49 +0000 (19:17 +0000)]
new siggen
ian [Thu, 12 Aug 2004 18:27:54 +0000 (18:27 +0000)]
allow stdin; opposite polarity
ian [Mon, 9 Aug 2004 21:14:20 +0000 (21:14 +0000)]
train-pic-prog-select
ian [Mon, 9 Aug 2004 01:46:41 +0000 (01:46 +0000)]
clean flasher
ian [Mon, 9 Aug 2004 01:45:12 +0000 (01:45 +0000)]
supposedly good program
ian [Mon, 9 Aug 2004 01:44:59 +0000 (01:44 +0000)]
make picprogs target
ian [Mon, 9 Aug 2004 00:16:25 +0000 (00:16 +0000)]
attempt at initial pic test prog
ian [Sun, 8 Aug 2004 20:26:47 +0000 (20:26 +0000)]
nicer args
ian [Sun, 8 Aug 2004 20:22:03 +0000 (20:22 +0000)]
seems to work
ian [Fri, 6 Aug 2004 01:30:21 +0000 (01:30 +0000)]
mitre
ian [Fri, 6 Aug 2004 01:00:01 +0000 (01:00 +0000)]
routed
ian [Fri, 6 Aug 2004 00:58:17 +0000 (00:58 +0000)]
trying finish route
ian [Fri, 6 Aug 2004 00:31:44 +0000 (00:31 +0000)]
at coredump
ian [Thu, 5 Aug 2004 23:17:25 +0000 (23:17 +0000)]
14 relays and stuff
ian [Thu, 5 Aug 2004 22:57:24 +0000 (22:57 +0000)]
trying all 14
ian [Thu, 5 Aug 2004 21:58:35 +0000 (21:58 +0000)]
first reverser seems ok
ian [Thu, 5 Aug 2004 21:30:07 +0000 (21:30 +0000)]
before import netlist first time
ian [Thu, 5 Aug 2004 21:11:41 +0000 (21:11 +0000)]
reversers pcb wip
ian [Sat, 24 Jul 2004 18:36:05 +0000 (18:36 +0000)]
thinner registration marks
ian [Sat, 24 Jul 2004 18:03:04 +0000 (18:03 +0000)]
registration marks
ian [Sun, 27 Jun 2004 19:24:02 +0000 (19:24 +0000)]
actual scales for -P
ian [Sun, 27 Jun 2004 18:55:39 +0000 (18:55 +0000)]
new test phys
ian [Sun, 13 Jun 2004 21:28:03 +0000 (21:28 +0000)]
indices in page corners
ian [Sun, 13 Jun 2004 20:25:25 +0000 (20:25 +0000)]
parameterise
ian [Sun, 13 Jun 2004 19:27:30 +0000 (19:27 +0000)]
do pages
ian [Sun, 13 Jun 2004 18:29:54 +0000 (18:29 +0000)]
testphys-ap.ps
ian [Sun, 13 Jun 2004 18:27:26 +0000 (18:27 +0000)]
testphys, for tracing, including scale option
ian [Thu, 27 May 2004 00:32:39 +0000 (00:32 +0000)]
suppress ts914
ian [Thu, 27 May 2004 00:30:29 +0000 (00:30 +0000)]
fix code for opamp
ian [Thu, 27 May 2004 00:29:03 +0000 (00:29 +0000)]
new circuits; new order
ian [Thu, 27 May 2004 00:28:49 +0000 (00:28 +0000)]
clean *~ and farn.*
ian [Thu, 27 May 2004 00:21:25 +0000 (00:21 +0000)]
old order
ian [Wed, 26 May 2004 01:07:36 +0000 (01:07 +0000)]
transient
ian [Wed, 26 May 2004 01:04:39 +0000 (01:04 +0000)]
oscillations
ian [Wed, 26 May 2004 00:53:17 +0000 (00:53 +0000)]
workingish
ian [Wed, 26 May 2004 00:50:37 +0000 (00:50 +0000)]
on semi
ian [Wed, 26 May 2004 00:36:12 +0000 (00:36 +0000)]
initial test, works
ian [Wed, 26 May 2004 00:28:47 +0000 (00:28 +0000)]
initial version
ian [Wed, 26 May 2004 00:24:39 +0000 (00:24 +0000)]
From Fairchild
ian [Sun, 23 May 2004 15:08:38 +0000 (15:08 +0000)]
fancier
ian [Sun, 23 May 2004 14:40:25 +0000 (14:40 +0000)]
divider table initial version seems okish
ian [Tue, 20 Apr 2004 22:13:28 +0000 (22:13 +0000)]
stuff
ian [Tue, 20 Apr 2004 21:05:00 +0000 (21:05 +0000)]
column heading on bom
ian [Tue, 20 Apr 2004 21:04:42 +0000 (21:04 +0000)]
some stuff to add
ian [Mon, 19 Apr 2004 00:20:44 +0000 (00:20 +0000)]
remove trailing 0s
ian [Mon, 19 Apr 2004 00:20:25 +0000 (00:20 +0000)]
add right number of blank lines
ian [Mon, 19 Apr 2004 00:20:08 +0000 (00:20 +0000)]
ignore bulkres.bom
ian [Mon, 19 Apr 2004 00:09:05 +0000 (00:09 +0000)]
clean rms boms etc; new bulkres stuff
ian [Mon, 19 Apr 2004 00:04:17 +0000 (00:04 +0000)]
implement ordering bom
ian [Mon, 19 Apr 2004 00:04:02 +0000 (00:04 +0000)]
allow tol in desc
ian [Sun, 18 Apr 2004 23:46:51 +0000 (23:46 +0000)]
searched for MRS25
ian [Sun, 18 Apr 2004 22:42:38 +0000 (22:42 +0000)]
sensible command-line parsing
ian [Sun, 18 Apr 2004 22:22:21 +0000 (22:22 +0000)]
can put stuff in basket
ian [Sun, 18 Apr 2004 20:37:13 +0000 (20:37 +0000)]
alarming - it hides your order in your browser state
ian [Sun, 18 Apr 2004 14:17:35 +0000 (14:17 +0000)]
uses LWP::UserAgent etc
ian [Sun, 18 Apr 2004 13:44:48 +0000 (13:44 +0000)]
not .pl
ian [Thu, 15 Apr 2004 00:05:52 +0000 (00:05 +0000)]
is wirewound
ian [Wed, 14 Apr 2004 23:57:06 +0000 (23:57 +0000)]
make circuit.bom with control.partlist
ian [Wed, 14 Apr 2004 23:55:50 +0000 (23:55 +0000)]
fixes; x-y board; sockets; others
~ijackson / trains.git / log