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service mode factory reset
[trains.git]
/
pcb
/
reversers.pcb
2004-09-12
ian
RPCL attaches before RPCI not after
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2004-09-09
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mounting holes 177thou = 4.5mm
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2004-09-07
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get rid of crappy unused 1 corner things
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2004-09-07
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move via away from edge by manual routing lots of stuff
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2004-09-04
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drc minoverlap 6
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2004-09-04
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solder resist tol is 5th from pad every pad
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2004-09-04
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change hole sizes for d25 and pfets
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2004-09-02
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square up header pins
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2004-09-02
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holes
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2004-09-02
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bigger indiv1 pins, routed
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2004-09-02
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routes again
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2004-09-02
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before fix up fet pins
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2004-09-02
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silk for point numbering
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2004-09-02
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trimmed again
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2004-09-02
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larger header-20
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2004-09-02
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bus connector and annotations
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2004-09-02
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mounting hole diagrams
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2004-09-02
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routes again
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2004-09-02
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truncate points plug and trim layout by 25th
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2004-09-02
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swap plug and socket
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2004-08-29
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reversers draft finished
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2004-08-29
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before shrink
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2004-08-29
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mounting holes placed
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2004-08-29
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mounting holes
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2004-08-26
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autoroutes again
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2004-08-26
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straighten silk texts
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2004-08-26
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layer id texts
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2004-08-26
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swap bus <-> indiv1
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2004-08-26
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ptd vertical mount
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2004-08-26
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indiv0-2 to indiv1-2 thick
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2004-08-26
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pc <-> pd
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2004-08-26
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pad/pin sizes
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2004-08-25
ian
rerun with only selected sides
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2004-08-25
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drc errors ok even when rerouting; resave ?
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2004-08-25
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drc errors ok even when rerouting
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2004-08-25
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manual fixup of drc errors
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2004-08-25
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with drc errors and rcs id
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2004-08-25
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autorouter makes drc errors
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2004-08-25
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before change d25 again
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2004-08-24
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helping autorouter
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2004-08-24
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before reorg d and manual stuff and...
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2004-08-24
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placement work, mounting gaps
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2004-08-24
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points connector varied
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2004-08-23
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wip nice
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2004-08-23
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furtling seems ok
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2004-08-23
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after fiddle manually
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2004-08-23
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before fiddle manually
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2004-08-23
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points
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2004-08-23
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much manual gnd/vcc routing
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2004-08-22
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pdw circuitry. need manual reverse0..5 routing
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2004-08-22
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wip routes
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2004-08-22
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largely routes
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2004-08-22
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netlist loads ok but still everything wip
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2004-08-22
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reversers pcb and netlist wip - netlist still broken
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2004-08-22
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some shuffling - wip
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2004-08-22
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has term0 connector
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2004-08-21
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reversers new connector wip
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2004-08-21
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turn real wip
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2004-08-21
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turn real wip
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2004-08-06
ian
mitre
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2004-08-06
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routed
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2004-08-06
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trying finish route
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2004-08-06
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at coredump
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2004-08-05
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14 relays and stuff
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2004-08-05
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trying all 14
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2004-08-05
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first reverser seems ok
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2004-08-05
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before import netlist first time
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2004-08-05
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reversers pcb wip
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diff to current
~ijackson / trains.git / history