From: ian <ian>
Date: Tue, 10 May 2005 22:30:35 +0000 (+0000)
Subject: documentation for processor memory map
X-Git-Url: http://www.chiark.greenend.org.uk/ucgi/~ijackson/git?a=commitdiff_plain;h=d05f891a0fe5794795c43ebda27de46dc492f56e;p=trains.git

documentation for processor memory map
---

diff --git a/cebpic/README.protocol b/cebpic/README.protocol
index 9f6fa26..b7f78b8 100644
--- a/cebpic/README.protocol
+++ b/cebpic/README.protocol
@@ -19,35 +19,92 @@ most significant bit first
 
 
 
-Reserved access bank locations
-==============================
-00h = WREG2
-01h = WREG3
-02h = WREG4
-
-
-Flash memory ID locations
-=========================
-
-(Buffer page 50 0000h reserved for NMRA)
-(Buffer page 40 0000h reserved for i2c)
-(Buffer page 50 0000h reserved for error codes)
-
-Byte 40 0000h
-		bits 7-5	= 000
-		bits 4-0        PIC number 
-				(guaranteed to be in range 0..31 inclusive)
-		
-
-Byte 40 0001h
-		bit 7		1 for the main PIC (#0)
-				0 otherwise
-		0-6		currently unused, set to 0
-
-Bytes 30 0000h - 3f ffffh
-		reserved for error messages, each 8 bytes long 
-		
-
+RAM (data) memory map
+=====================
+
+The data memory map (for PIC18F458) looks like this:
+
+ 0x000-0x05f    Access bank RAM - RAM locations accessible via
+                 access bank instructions; also form part of
+                 RAM page 0
+ 0x060-0x0ff    Remainder of RAM page 0, accessible only via correct
+                 BSR setting (ie, BSR==0), INDF, etc.
+
+ 0x100-0x1ff    RAM page 1, accessible only via bank switching etc.
+ 0x200-0x2ff    RAM page 2, accessible only via bank switching etc.
+ 0x300-0x3ff    RAM page 3, accessible only via bank switching etc.
+ 0x400-0x4ff    RAM page 4, accessible only via bank switching etc.
+ 0x500-0x5ff    RAM page 5, accessible only via bank switching etc.
+
+ 0x600-0xeff    Nothing here, don't try to access.
+
+ 0xf00-0xf5f    SFR's (memory-mapped peripherals etc.) accessible
+                 only via correct BSR, INDF, etc - but these are only
+                 the CAN SFR's and we do not use the CAN controller.
+ 0xf60-0xfff    SFR's accessible via access bank (also form part
+                 of RAM page 15).
+
+
+See common.inc for actual uses of the RAM areas.
+
+
+Program (flash etc.) memory map
+===============================
+
+Program memory map (for PIC18F458) looks like this:
+
+  0x00 0000-    Program memory
+  0x00 7fff      Contains actual program instructions and can also
+                 contain preprogrammed data provided via special .asm
+                 files.  Notable contents and addresses:
+                   0x00 0000  reset vector
+                   0x00 0008  high-priority interrupt vector
+                   0x00 0018  low-priority interrupt vector
+                 See common.inc for some special tables in here, for
+                 morse messages, pin/hardware-object definitions, etc.
+		 
+  0x20 0000-	ID locations
+  0x20 0007      Programming which varies per PIC.  Programmed by
+                 idlocs*.asm which are made by make-idlocs and
+                 included in perpic*.hex.  Contents:
+
+                0x20 0000
+                  bits 7-5 = 000
+                  bits 4-0 = PIC number (guaranteed to be
+                             in the range 0..31 inclusive)
+                0x20 0001
+                  bit 7     = 1 for the main PIC (#0)
+                              0 otherwise
+                  bits 0-6  = currently unused, set to 0
+
+                0x20 0002-  } not currently used,
+                0x20 0007   }  may contain anything
+		 
+  0x30 0000-    Hardware configuration
+  0x30 000f      Defines (clock source, WDT operation, etc.)
+                 Probably best not to touch.  `config.asm' provides
+                 correct contents, which is included in *-withcfg.hex
+                 and perpic*.hex.
+		 
+  0x3f fffe-	Hardware device ID
+  0x3f ffff      Fixed at manufacturing time; can be read to discover
+                 hardware type and version (probably not very useful)
+
+  0xf0 0000-    EEPROM data area
+  0xf0 00ff      Not currently used by us
+
+  0x01 0000-    } These locations, not listed above,       
+  0x1f ffff     }   do not correspond to anything - there  
+  0x20 0008-    }   is no hardware or memory in the chip   
+  0x2f ffff     }   at these locations.                    
+  0x30 0010-    }
+  0x3f fffd     } Accessing them isn't useful
+  0x40 0000-    }   and should probably be avoided.
+  0xef ffff     }
+
+
+(Buffer page 50 0000h reserved for NMRA)    XXXX these look wrong
+(Buffer page 40 0000h reserved for i2c)     XXXX   -iwj
 
 
 
diff --git a/cebpic/common.inc b/cebpic/common.inc
index 51b51ed..fd58783 100644
--- a/cebpic/common.inc
+++ b/cebpic/common.inc
@@ -9,9 +9,28 @@
 	include         /usr/share/gputils/header/p18f458.inc
         radix           dec 
 
+;==============================
+; RAM memory usage
+
+; Access bank locations
+WREG2		equ	0x000
+WREG3		equ	0x001
+WREG4		equ	0x002
+
+;==============================
+; Program (flash) memory regions
+
+; Actual code starts at 0 with the reset and interrupt vectors and
+; then the program proper.
+
+;--------------------
+; Area filled in by morse-auto.asm (see morse-auto.asm-gen for details)
 morse_messages_start	equ	0x4000
 morse_messages_end	equ	0x4400
 
+;--------------------
+; Areas filled in by ../layout/ours-pindata.asm
+;  (see pindata.inc for details)
 pt_pic_data		equ	0x6000
 pt_port_data		equ	0x6100
 pt_bit_data		equ	0x6200
@@ -28,6 +47,7 @@ pt_num_max		equ	256
 sense_num_max		equ	256
 reverse_num_max		equ	256
 
+
 ;----------------------------------------
 ; ifbit1(REGISTER,BITNUMBER)
 ;       executes the next instruction but only if bit BITNUMBER