From: ian Date: Sun, 22 Aug 2004 22:42:40 +0000 (+0000) Subject: wip routes X-Git-Url: http://www.chiark.greenend.org.uk/ucgi/~ijackson/git?a=commitdiff_plain;h=8e48ea1c5eb6a6c7fcb04ede2b90681a3fa2ee62;p=trains.git wip routes --- diff --git a/pcb/reversers.pcb b/pcb/reversers.pcb index d59fe4e..081d1d4 100644 --- a/pcb/reversers.pcb +++ b/pcb/reversers.pcb @@ -1,12 +1,12 @@ # release: pcb-bin 1.99p -# date: Sun Aug 22 23:25:16 2004 +# date: Sun Aug 22 23:42:24 2004 # user: ian (Ian Jackson) # host: anarres.relativity.greenend.org.uk PCB["reversers.pcb" 1410000 355000] Grid[2500.00000000 0 0 1] -Cursor[469099 351824 5.297566] +Cursor[584178 175912 3.297566] Thermal[0.500000] DRC[809 400 800 800] Flags(0x0000000000001e51) @@ -777,7 +777,7 @@ Symbol['~' 1200] Element[0x00000000 "resistor_axial" "RS2" "500" 350000 147500 -1400 -2000 1 100 0x00000000] ( Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000101] - Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000001] + Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000201] ElementLine [-4100 0 4100 0 1000] ElementLine [4100 -25000 4100 0 1000] ElementLine [-4100 -25000 4100 -25000 1000] @@ -913,7 +913,7 @@ Element[0x00000000 "" "PT0" "" 1155000 110000 -7500 -10000 0 100 0x00000000] Element[0x00000000 "resistor_axial" "RS0" "500" 500000 147500 -1400 -2000 1 100 0x00000000] ( Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000101] - Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000001] + Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000201] ElementLine [-4100 0 4100 0 1000] ElementLine [4100 -25000 4100 0 1000] ElementLine [-4100 -25000 4100 -25000 1000] @@ -925,8 +925,8 @@ Element[0x00000000 "resistor_axial" "RS0" "500" 500000 147500 -1400 -2000 1 100 Element[0x00000000 "resistor_axial" "RS3" "500" 275000 147500 -1400 -2000 1 100 0x00000000] ( - Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000101] - Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000001] + Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000301] + Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000201] ElementLine [-4100 0 4100 0 1000] ElementLine [4100 -25000 4100 0 1000] ElementLine [-4100 -25000 4100 -25000 1000] @@ -1087,7 +1087,7 @@ Element[0x00000000 "" "RLY0" "" 450000 90000 12500 25000 1 100 0x00000000] Pin[30000 0 6000 3000 6000 2800 "" "16" 0x00000001] Pin[30000 30000 6000 3000 6000 2800 "" "13" 0x00000001] Pin[0 30000 6000 3000 6000 2800 "" "4" 0x00000001] - Pin[30000 70000 6000 3000 6000 2800 "" "9" 0x00000001] + Pin[30000 70000 6000 3000 6000 2800 "" "9" 0x00000201] Pin[0 50000 6000 3000 6000 2800 "" "6" 0x00000001] Pin[30000 50000 6000 3000 6000 2800 "" "11" 0x00000001] Pin[0 70000 6000 3000 6000 2800 "" "8" 0x00000001] @@ -1166,11 +1166,11 @@ Element[0x00000000 "Header connector, ribbon cable numbering" "INDIV1" "HEADER34 Element[0x00000000 "generic" "OC0" "DIL 16" 522500 90000 17000 5000 3 100 0x00000000] ( - Pin[0 0 6000 3000 6600 2800 "1" "1" 0x00000101] + Pin[0 0 6000 3000 6600 2800 "1" "1" 0x00000301] Pin[0 10000 6000 3000 6600 2800 "2" "2" 0x00000001] - Pin[0 20000 6000 3000 6600 2800 "3" "3" 0x00000001] + Pin[0 20000 6000 3000 6600 2800 "3" "3" 0x00000201] Pin[0 30000 6000 3000 6600 2800 "4" "4" 0x00000001] - Pin[0 40000 6000 3000 6600 2800 "5" "5" 0x00000001] + Pin[0 40000 6000 3000 6600 2800 "5" "5" 0x00000201] Pin[0 50000 6000 3000 6600 2800 "6" "6" 0x00000001] Pin[0 60000 6000 3000 6600 2800 "7" "7" 0x00000001] Pin[0 70000 6000 3000 6600 2800 "8" "8" 0x00000001] @@ -1396,8 +1396,8 @@ Element[0x00000000 "" "BR4" "" 155000 185000 12500 -5000 0 100 0x00000000] Element[0x00000000 "resistor_axial" "RS4" "500" 200000 147500 -1400 -2000 1 100 0x00000000] ( - Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000101] - Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000001] + Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000301] + Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000201] ElementLine [-4100 0 4100 0 1000] ElementLine [4100 -25000 4100 0 1000] ElementLine [-4100 -25000 4100 -25000 1000] @@ -1410,7 +1410,7 @@ Element[0x00000000 "resistor_axial" "RS4" "500" 200000 147500 -1400 -2000 1 100 Element[0x00000000 "" "BR2" "" 305000 185000 12500 -5000 0 100 0x00000000] ( Pin[0 0 6000 2000 6006 3500 "" "1" 0x00000001] - Pin[42500 0 6000 2000 6006 3500 "" "2" 0x00000001] + Pin[42500 0 6000 2000 6006 3500 "" "2" 0x00000201] Pin[42500 42500 6000 2000 6006 3500 "" "3" 0x00000001] Pin[0 42500 6000 2000 6006 3500 "" "4" 0x00000001] ElementLine [0 -10000 52500 -10000 1000] @@ -1428,8 +1428,8 @@ Element[0x00000000 "" "BR2" "" 305000 185000 12500 -5000 0 100 0x00000000] Element[0x00000000 "resistor_axial" "RS5" "500" 125000 147500 -1400 -2000 1 100 0x00000000] ( - Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000101] - Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000001] + Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000301] + Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000201] ElementLine [-4100 0 4100 0 1000] ElementLine [4100 -25000 4100 0 1000] ElementLine [-4100 -25000 4100 -25000 1000] @@ -1479,8 +1479,8 @@ Element[0x00000000 "" "BR1" "" 380000 185000 12500 -5000 0 100 0x00000000] Element[0x00000000 "resistor_axial" "RS1" "500" 425000 147500 -1400 -2000 1 100 0x00000000] ( - Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000101] - Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000001] + Pin[0 12500 5000 3000 5600 2000 "1" "1" 0x00000301] + Pin[0 -37500 5000 3000 5600 2000 "2" "2" 0x00000201] ElementLine [-4100 0 4100 0 1000] ElementLine [4100 -25000 4100 0 1000] ElementLine [-4100 -25000 4100 -25000 1000] @@ -1917,9 +1917,9 @@ Rat[612500 97500 1 580000 177500 1 0x00000010] Rat[580000 177500 1 552500 180000 1 0x00000010] Rat[612500 57500 1 580000 187500 1 0x00000010] Rat[580000 187500 1 552500 200000 1 0x00000010] -Rat[507500 172500 0 512500 167500 0 0x00000010] -Rat[510000 180000 0 522500 180000 1 0x00000010] -Rat[505000 200000 0 522500 200000 1 0x00000010] +Rat[512500 167500 0 507500 172500 0 0x00000010] +Rat[522500 180000 1 510000 180000 0 0x00000010] +Rat[522500 200000 1 505000 200000 0 0x00000010] Rat[612500 17500 1 980000 205000 1 0x00000010] Rat[980000 205000 1 1060000 192000 1 0x00000010] Layer(1 "component") @@ -2391,85 +2391,85 @@ NetList() Connect("OC0-8") Connect("OC1-2") Connect("OC1-4") - Connect("TERM-2") Connect("BR0-4") Connect("BR1-4") Connect("BR2-4") Connect("BR3-4") Connect("BR4-4") Connect("BR5-4") + Connect("TERM-2") ) Net("q0" "Fat") ( - Connect("TERM-4") Connect("RLY0-4") + Connect("TERM-4") ) Net("q1" "Fat") ( - Connect("TERM-6") Connect("RLY1-4") + Connect("TERM-6") ) Net("q2" "Fat") ( - Connect("TERM-8") Connect("RLY2-4") + Connect("TERM-8") ) Net("q3" "Fat") ( - Connect("TERM-10") Connect("RLY3-4") + Connect("TERM-10") ) Net("q4" "Fat") ( - Connect("TERM-12") Connect("RLY4-4") + Connect("TERM-12") ) Net("q5" "Fat") ( - Connect("TERM-14") Connect("RLY5-4") + Connect("TERM-14") ) Net("qmid0" "Fat") ( - Connect("RS0-2") - Connect("BR0-2") Connect("RLY0-6") Connect("RLY0-9") + Connect("BR0-2") + Connect("RS0-2") ) Net("qmid1" "Fat") ( - Connect("RS1-2") - Connect("BR1-2") Connect("RLY1-6") Connect("RLY1-9") + Connect("BR1-2") + Connect("RS1-2") ) Net("qmid2" "Fat") ( - Connect("RS2-2") - Connect("BR2-2") Connect("RLY2-6") Connect("RLY2-9") + Connect("BR2-2") + Connect("RS2-2") ) Net("qmid3" "Fat") ( - Connect("RS3-2") - Connect("BR3-2") Connect("RLY3-6") Connect("RLY3-9") + Connect("BR3-2") + Connect("RS3-2") ) Net("qmid4" "Fat") ( - Connect("RS4-2") - Connect("BR4-2") Connect("RLY4-6") Connect("RLY4-9") + Connect("BR4-2") + Connect("RS4-2") ) Net("qmid5" "Fat") ( - Connect("RS5-2") - Connect("BR5-2") Connect("RLY5-6") Connect("RLY5-9") + Connect("BR5-2") + Connect("RS5-2") ) Net("reverse0" "Signal") ( @@ -2512,44 +2512,44 @@ NetList() Net("rly_v12" "Power") ( Connect("BUS-17") - Connect("ULN-10") - Connect("CULN-2") Connect("RLY0-1") Connect("RLY1-1") Connect("RLY2-1") Connect("RLY3-1") Connect("RLY4-1") Connect("RLY5-1") + Connect("ULN-10") + Connect("CULN-2") ) Net("rlydrv0" "Signal") ( - Connect("ULN-16") Connect("RLY0-16") + Connect("ULN-16") ) Net("rlydrv1" "Signal") ( - Connect("ULN-15") Connect("RLY1-16") + Connect("ULN-15") ) Net("rlydrv2" "Signal") ( - Connect("ULN-14") Connect("RLY2-16") + Connect("ULN-14") ) Net("rlydrv3" "Signal") ( - Connect("ULN-13") Connect("RLY3-16") + Connect("ULN-13") ) Net("rlydrv4" "Signal") ( - Connect("ULN-12") Connect("RLY4-16") + Connect("ULN-12") ) Net("rlydrv5" "Signal") ( - Connect("ULN-11") Connect("RLY5-16") + Connect("ULN-11") ) Net("sense0" "Signal") ( @@ -2589,33 +2589,33 @@ NetList() ) Net("sensei0" "Signal") ( - Connect("RS0-1") Connect("OC0-1") + Connect("RS0-1") ) Net("sensei1" "Signal") ( - Connect("RS1-1") Connect("OC0-3") + Connect("RS1-1") ) Net("sensei2" "Signal") ( - Connect("RS2-1") Connect("OC0-5") + Connect("RS2-1") ) Net("sensei3" "Signal") ( - Connect("RS3-1") Connect("OC0-7") + Connect("RS3-1") ) Net("sensei4" "Signal") ( - Connect("RS4-1") Connect("OC1-1") + Connect("RS4-1") ) Net("sensei5" "Signal") ( - Connect("RS5-1") Connect("OC1-3") + Connect("RS5-1") ) Net("spare0" "Signal") ( @@ -2655,7 +2655,6 @@ NetList() ) Net("t" "Signal") ( - Connect("TERM-1") Connect("RLY0-8") Connect("RLY0-11") Connect("RLY1-8") @@ -2668,35 +2667,36 @@ NetList() Connect("RLY4-11") Connect("RLY5-8") Connect("RLY5-11") + Connect("TERM-1") ) Net("t0" "Fat") ( - Connect("TERM-3") Connect("RLY0-13") + Connect("TERM-3") ) Net("t1" "Fat") ( - Connect("TERM-5") Connect("RLY1-13") + Connect("TERM-5") ) Net("t2" "Fat") ( - Connect("TERM-7") Connect("RLY2-13") + Connect("TERM-7") ) Net("t3" "Fat") ( - Connect("TERM-9") Connect("RLY3-13") + Connect("TERM-9") ) Net("t4" "Fat") ( - Connect("TERM-11") Connect("RLY4-13") + Connect("TERM-11") ) Net("t5" "Fat") ( - Connect("TERM-13") Connect("RLY5-13") + Connect("TERM-13") ) ) diff --git a/reversers-netlist.pl b/reversers-netlist.pl index d43b440..3966007 100755 --- a/reversers-netlist.pl +++ b/reversers-netlist.pl @@ -189,14 +189,6 @@ assignpins('INDIV1',25,@indiv); # 25-way D o('l_gnd', Power, 'CPIC0-1 CPIC1-1'); o('l_vcc', Power, 'CPIC0-2 CPIC1-2'); -assignpins(qw(ULN 18 - :11 rlydrv5..0 - :8- reverse5..0 rly_gnd rly_gnd - :9 rly_gnd - :10 rly_v12)); - -assignpins(qw(CULN 2 rly_gnd rly_v12)); - sub assignpins_multi ($$@) { # Args are linemin linemax linesperchip and a list like for assignpins # assignpins is done several times to handle all of the lines. @@ -233,11 +225,6 @@ sub assignpins_multi ($$@) { } } -assignpins_multi(0,5, 1, - qw(RS@ 2 - 1 qmid@ - 2 sensei@)); - assignpins_multi(0,5, 4, qw(OC@ 16@@8 :1+2 sensei<..> @@ -245,21 +232,6 @@ assignpins_multi(0,5, 4, :-1-2 l_gnd*& :-0-2 sense<..>)); -assignpins(qw(TERM 14 - 1 t q - :3+2 t0..5 - :4+2 q0..5)); - -assignpins(qw(RAS 9 - l_vcc - :2 sense0..5)); - -assignpins_multi(0,5, 1, - qw(BR@ 4 - :1+2 sshort@*2 - :2 qmid@ - :4 q)); - assignpins_multi(0,5, 1, qw(RLY@ 16 :1 rly_v12 @@ -271,26 +243,50 @@ assignpins_multi(0,5, 1, :13 t@ :16 rlydrv@)); +assignpins_multi(0,5, 1, + qw(BR@ 4 + :1+2 sshort@*2 + :2 qmid@ + :4 q)); + + foreach $iter (0..5) { o("t$iter", Fat, ''); o("q$iter", Fat, ''); o("qmid$iter", Fat, ''); } +sub data_fin () { + return if !length $data_accum; + local ($_); + if ($data_accum =~ s,^(\d+)\-(\d+)/(\d+)\s+,,) { + assignpins_multi($1,$2,$3, split /\s+/, $data_accum); + } else { + assignpins(split /\s+/, $data_accum); + } + undef $data_accum; +} + while () { next if m/^\#/; next unless m/\S/; chomp; - s/^\s+//; s/\s+$//; + if (s/^\s+//) { + die unless length $data_accum; + $data_accum .= " ".$_; + next; + } + data_fin(); if (m/^([a-z]\S+)\s+(\S+)(\s+(\S.*\S))?$/) { o($1,$2,"%s",$3); - } elsif (m/^[A-Z].*/) { - assignpins(split /\s+/); + } elsif (m/^[A-Z].*/ || m,^\d+\-\d+/\d+\s+[A-Z],) { + $data_accum= $_; } else { die "$_ ?"; } } +data_fin(); # Firstly, assemble # $othernames{$sn}{$sn2}=1 iff $sn and $sn2 are mentioned together @@ -384,3 +380,24 @@ l_gnd Power l_vcc Power rly_gnd Power rly_v12 Power + +TERM 14 + 1 t q + :3+2 t0..5 + :4+2 q0..5 + +ULN 18 + :11 rlydrv5..0 + :8- reverse5..0 rly_gnd rly_gnd + :9 rly_gnd + :10 rly_v12 + +CULN 2 + rly_gnd rly_v12 + +RAS 9 + l_vcc + :2 sense0..5 + +0-5/1 RS@ 2 + sensei@ qmid@