From: ian Date: Tue, 24 Aug 2004 19:28:15 +0000 (+0000) Subject: fancier netlist generation X-Git-Url: http://www.chiark.greenend.org.uk/ucgi/~ijackson/git?a=commitdiff_plain;h=15558456f940acdd14e9cb968886b5ac4e6db99b;p=trains.git fancier netlist generation --- diff --git a/reversers-netlist.pl b/reversers-netlist.pl index fa3538d..d5bc79b 100755 --- a/reversers-netlist.pl +++ b/reversers-netlist.pl @@ -21,19 +21,19 @@ sub unpack_iter_list ($$@) { # p allow only partial specification # o return array of pins (first entry is undef) in order # instead of array of { Pin =>, Action => } - my ($currentpin, @expanded, $base,$start,$end,$step,$i, @done,@out); - my ($backwards, $sign, $jump, $modulo, $usepin); + my (@expanded, @done, @out); + my ($i); local ($_); @expanded= (); foreach $_ (@in) { if (m/^(\w*[A-Za-z])(\d+)\.\.(\d+)$/) { - ($base,$start,$end)=($1,$2,$3); - $step= $start<$end ? 1 : $start>$end ? -1 : die; + my ($base,$start,$end)=($1,$2,$3); + my ($step)= $start<$end ? 1 : $start>$end ? -1 : die; for ($i=$start; $i!=$end+$step; $i+=$step) { push @expanded, $base.$i; } } elsif (m/^(\w+)\*(\d+)/) { - ($base,$end)=($1,$2); + my ($base,$end)=($1,$2); die unless $end >= 1; for ($i=1; $i<=$end; $i++) { push @expanded, $base; @@ -42,26 +42,37 @@ sub unpack_iter_list ($$@) { push @expanded, $_; } } - $step= 1; - $currentpin= 1; + my $start= 1; + my $step= 1; + my $jump= 0; + my $modulo= ''; + my $counter= 0; + my ($usepin, $remainder, $quotient); foreach $_ (@expanded) { + if (!length $modulo) { + $remainder= 0; + $quotient= $counter; + } else { + $remainder= $counter % $modulo; + $quotient= ($counter-$remainder) / $modulo; + } + $usepin= + ($start + + $step * $quotient + + $jump * $remainder); if (m/^\d+$/) { - die "$_ != $currentpin $max (@in) (@expanded)" - if $currentpin ne $&; - } elsif (m/^\:(\-?)(\d+)(?:([-+]\d+)|([-+])|)(?:\%(\d+)\/(\d+))?$/) { - ($backwards,$start,$step,$sign,$jump,$modulo)=($1,$2,$3,$4,$5,$6); - $currentpin= length $backwards ? $max-$start : $start; - $step= length $step ? $step : length $sign ? $sign.'1' : 1; + die "$_ != $usepin $max (@in) (@expanded)" + if $usepin ne $&; + } elsif ( + m/^\:(\-?)(\d+)(?:([-+]\d+)|([-+])|)(?:\%(\-?\d+)\/(\d+))?$/ + ) { + my ($back,$base,$stepval,$sign)=($1,$2,$3,$4); + ($jump,$modulo)=($5,$6); + $start= length $back ? $max-$base : $base; + $step= length $stepval ? $stepval : length $sign ? $sign.'1' : 1; + $counter= 0; } else { if ($_ ne '-') { - $usepin= $currentpin; - if (length $jump) { - $usepin--; - my ($remainder) = $usepin % $modulo; - $usepin= ($usepin - $remainder) / $modulo + - $remainder * $jump; - $usepin++; - } die "$usepin<1 $_ $max (@in) (@expanded)" if $usepin < 1; die "$usepin>$max $_ $max (@in) (@expanded)" @@ -71,7 +82,7 @@ sub unpack_iter_list ($$@) { push @out, { Pin => $usepin, Action => $_ }; $done[$usepin]= $_; } - $currentpin += $step; + $counter++; } } if ($options !~ m/p/) { @@ -220,8 +231,8 @@ sub assignpins_multi ($$@) { $linesthischip= $line_high - $line_low + 1; @ol= @il; map { - s/^(.*)\@\@(.*)$/ $full_chip ? $1 : $2 /ge; - s/\@/ $chipno /ge; + s/^(.*)\=\=(.*)$/ $full_chip ? $1 : $2 /ge; + s/\=/ $chipno /ge; s/\/ $line_high /ge; s/\&/ $linesthischip /ge; @@ -233,20 +244,20 @@ sub assignpins_multi ($$@) { } assignpins_multi(0,5, 1, - qw(RLY@ 16 + qw(RLY= 16 :1 rly_v12 - :4 q@ - :6 qmid@ + :4 q= + :6 qmid= :8 t - :9 qmid@ + :9 qmid= :11 t - :13 t@ - :16 rlydrv@)); + :13 t= + :16 rlydrv=)); assignpins_multi(0,5, 1, - qw(BR@ 4 - :1+2 sshort@*2 - :2 qmid@ + qw(BR= 4 + :1+2 sshort=*2 + :2 qmid= :4 q)); @@ -375,6 +386,52 @@ foreach $canon (sort keys %propernet) { or die $!; } +# Syntax: +# +# netspec Type CHIP-pin ... +# +# CHIP npins ...pin-spec-item... +# ...pin-spec-item... +# defines some pins from CHIP which has pins 1..npins +# +# minline-maxline/perchip CHIP pins ...pin-spec-item... +# ...pin-spec-item... +# Defines some pins from several chips. See assignpins_multi comment. +# +# CHIP is [A-Z][A-Z0-9]* +# +# netspec is net[,net]* and indicates that all the nets are aliases for same +# net even if not mentioned together anywhere else +# +# net is [a-z][a-z0-9_]* +# +# pin-spec-item is one of +# +# netspec assigns next pin to netspec +# +# net\d+..\d+ assigns next several pins to sequentially named nets +# nets will be net\d+ where numbers will go from first +# \d+ to 2nd \d+ in pin-spec-item inclusive (whether +# up or down) +# +# pin asserts that next pin number to assign would be pin +# +# :start[step][%jump/modulo] +# specifies that the next pin to assign will be start, +# and what the following pin will be to assign, and so +# on in arithmetic sequence indefinitely until the +# next :start[... etc. +# start can be pin (meaning to start with pin) +# or -backpin meaning to start with npins-backpin +# step can be + or - to indicate +1 or -1 or +# a possibly negative number +# %jump/modulo means don't generate a simple +# arithmetic sequence; instead, generate +# modulo arithmetic sequences starting at +# start, start+jump, ... start+(modulo-1)*jump +# and then interleave the sequences to +# generate the sequence of pins to assign + __DATA__ l_gnd Power l_vcc Power @@ -394,22 +451,22 @@ ULN 18 CULN 2 rly_gnd rly_v12 CAC05 2 l_gnd l_vcc -0-1/1 CPIC@ 2 l_gnd l_vcc +0-1/1 CPIC= 2 l_gnd l_vcc RAS 9 l_vcc :2 sense3..0 sense5..4 - perpicled -0-5/4 OC@ 16@@8 +0-5/4 OC= 16==8 :1+2 sensei<..> :2+2 q*& :-1-2 l_gnd*& :-0-2 sense<..> -0-5/1 RS@ 2 - sensei@ qmid@ +0-5/1 RS= 2 + sensei= qmid= AC05 14 :8+ @@ -431,12 +488,13 @@ RPCI 2 icsp_pc icsp_pcq RPCL 2 icsp_pc l_gnd RPCPT 2 icsp_pc ptgate1 -0-17/1 PTFET@ 3 ptgate@ ptdrain@ cdu_gnd -0-17/1 PTD@ 2 cdu_out ptdrain@ -2-17/8 RAP@ 16 :1 pt<..> :-0- ptgate<..> +0-17/1 PTFET= 3 ptgate= ptdrain= cdu_gnd +0-17/1 PTD= 2 cdu_out ptdrain= +2-17/8 RAP= 16 :1 pt<..> :-0- ptgate<..> POINTS 25 - :25-1%13/2 ptdrain0..17 + :25-1%-13/2 ptdrain0..17 + TS912 8 :1 ledmid_red perpicled led_reflow