compiles

diff --git a/cebpic/i2c-test-reply.asm b/cebpic/i2c-test-reply.asm
index f191ea1816695df9ad37240006d277e12b340e22..82ec2a984fa8e816f4967a62e838ecdf2f36fa00 100644 (file)
--- a/cebpic/i2c-test-reply.asm
+++ b/cebpic/i2c-test-reply.asm
@@ -440,15 +440,14 @@ vector_interrupt_low
 ; to the relevant ISR.  That routine will return with retfie and if
 ; there was another interrupt we will re-enter, which is OK.
 
-       btfsc   PIR1,SSPIF,0    ; check if MSSP interrupt generated, if so
+;      btfsc   PIR1,SSPIF,0    ; check if MSSP interrupt generated, if so
 ;      goto    i2c_isr         ; I2C ISR will check whether master or slave
-       goto    panic           ; nothing should generate these ATM....
 
         btfsc   PIR1,5,0        ; check for serial receive interrupt
        goto    serial_rx_isr   ; receive serial
 
        debug   'L'             ; else panic - interrupt but don't know why
-       goto    panic
+       panic   morse_IL
 
 ;----------------------------------------
 enable_interrupts
@@ -522,14 +521,14 @@ serial_rx_isr
        debug   'f'
 
        ifbit1  SSPCON2,ACKSTAT         ; check for ack from slave (=0), if no
-       goto    panic                   ; then panic, else
+       panic   morse_SA                ; then panic, else
 
        debug   'g'
 
        movff   RCREG,SSPBUF            ; copy byte from serial to i2c buffer
        call    wait_for_i2c_interrupt
        btfsc   SSPCON2,ACKSTAT,0       ; check for ack from slave (=0), if no
-       goto    panic                   ; then panic, else
+       panic   morse_SD                ; then panic, else
        bsf     SSPCON2,PEN,0           ; i2c STOP
        call    wait_for_i2c_interrupt