detector on detector seems to spuriously set B1 or B2 or at least
panic DR when we honour it
+point setting doesn't seem to work
+ residual stuff from CDU is present and changes pt0 when you
+ * turn on
+ * say `+' to master to turn on CDU
+ * switch to programming mode
+ pt0 on pic2 is the one nearest the switch box, moving to hacker's right
+ (we think - I haven't checked this yet)
+
crash readout: master i2c should go into known state
layout polarity diagram colourful segment encoding:
intrh_fsr0_save ; point_set_pin uses FSR0, see below
rcall point_set_pin
intrh_fsr0_restore
+ panic morse_UP
clr_f TMR3L ; also copies TMR3H into actual timer register
bs_f T3CON, TMR3ON
bra_z point_nonexistent
mov_ff INDF0, FSR0L ; W = bit, FSR0L -> LAT*
set_f FSR0H ; FSR0 -> LAT*, W = bit (still)
- mov_ff BSR,FSR0H;qq
ior_wff INDF0 ; pin = H
return
com_fw POSTDEC0 ; W = ~bit, FSR0 -> &LAT*
mov_ff INDF0, FSR0L ; W = ~bit, FSR0L -> LAT*
set_f FSR0H ; FSR0 -> LAT*, W = bit (still)
- mov_ff BSR,FSR0H;qq
and_wff INDF0 ; pin = H
point_set_pin_hl
tst_f_ifnz FSR0L ; err, did we just write to 0xf00 ?
mov_wf TBLPTRH ; TBLPTR* -> point port/bit data
set_f FSR2H ; FSR2 -> some SFR, will point to LAT/TRIS
- mov_ff BSR,FSR2H;qq
mov_lfsr bitnum2bit+7, 1 ; FSR1 -> bitnum2bit+7
mov_lfsr ptix2latbit-1, 0 ; FSR0 -> last bit (and previous LAT*)
swap_fw TABLAT ; W = bitnum4 || portnum4
and_lw 0x0f ; W = portnum4
- add_lw qqLATA & 0xff ; W = LAT*
+ add_lw LATA & 0xff ; W = LAT*
mov_wf POSTINC0 ; LAT*[this] := LAT, FSR0 -> bit[this]
mov_wf FSR2L ; FSR2 -> LAT*
and_wff INDF2 ; LAT* &= ~bit, ie pin set to L (still Z)
pin_vh pall_pt0reverse ; but pt0 pin is backwards, set to H
; (still Z, unless we've done this already)
- mov_lw qqTRISA-qqLATA
+ mov_lw TRISA-LATA
add_wff FSR2L ; FSR2 -> TRIS*
com_fw INDF1 ; W = ~bit
and_wff INDF2 ; TRIS* &= ~bit, ie pin set to not Z