panicst_ferroerr equ 4
panicst_writeslave equ 3
panicst_i2cmours equ 2
-panicst_i2cmenable equ 2
+panicst_i2cmenable equ 1
panic_valcount res 1
;----------
panicst_oerrferr
- dec_fw RCREG
+ mov_fw RCREG
+ xor_lw 0x11
+ bra_z panic_reset
+ xor_lw 0x10 ^ 0x11
bra_nz panicd_serialrx_err_loop
; yay! host ack'd ferr/oerr
bc_f panicst, panicst_ferroerr
mov_fw RCREG ; read RCREG } (see PIC18FXX8 DS p182)
bs_f RCSTA, RCEN ; reenable }
panicd_serialrx_err_loop
- bt_f_if0 PIR1, RCIF ; wait for a byte 0x01 to ack the overrun/error
+ bt_f_if0 PIR1, RCIF ; wait for a byte 0x10 to ack the overrun/error
bra panicd_serialrx_err_loop
;...
;----------
;----------
write_ifnot_00
bt_f_if0 panicst, panicst_acked ; well, ignore that !
- return
+ bra write_only_tellmode
; OK, we have an instruction:
bt_w_if1 7 ; huh?
bt_w_if1 6
bra panic_crashread_setpointer
bt_f_if0 idloc1,idloc1_master
- return ; all the remaining options are for master only
+ bra write_ifnot0_ifnotmaster
+ ; the next few options are for master only:
+
bt_w_if1 5
bra write_if_master_slaveselect
bt_w_if1 4
bra write_if_master_masterread
+ bt_w_if0 3
bra write_if_master_slaveread
- return ; huh ?
+;...
+write_ifnot0_ifnotmaster
+ xor_lw 0x09
+ bra_z panic_reset
+ xor_lw 0x09
+;...
+write_only_tellmode
+ xor_lw 0x0a
+ bra_z panic_tellmode
+ ; nope, well, we ignore it
+ return
;----------
panic_crashread_setpointer
and_lw 0x3f
ior_wfw PRODL
mov_wf FSR1L
+panic_noop
+ return
+
+;======================================================================#
+; SPECIAL COMMANDS 0x08..0x0f
+
+;----------
+panic_reset
+ reset
+
+;----------
+panic_tellmode
+ bt_f_if0 idloc1,idloc1_master
return
+ mov_lw 0x0b
+ bc_f panicst, panicst_acked
+ goto serial_write_char
;======================================================================
; MASTER READOUT AND MASTER READOUT OF SLAVES
mov_lw ' '
goto serial_write_char
+;----------
+pan_i2cmu_slave_no_ack
+ i2cpanic morse_SP
+
;======================================================================
; SLAVE I2C