;----------------------------------------------------------------------
; COMMON INCLUDES and BOILERPLATE
- include /usr/share/gputils/header/p18f458.inc
+ include p18f458.inc
radix dec
include panic.inc
include morse+auto.inc
include program+clocks.inc
include i2clib.incm
+tickdiv equ 16
+tickdiv_us equ tick_us * tickdiv
+
;----------------------------------------------------------------------
; Common conventions for function register notation:
-; Master Slave
+; Master Slave
; Registers etc.
-; W Trashed Trashed
-; STATUS Trashed Trashed
-; BSR Not used Not used
-; t Low ISR Low ISR
-; u Low ISR Low ISR
-; TBLPTR*,TABLAT Low ISR Low ISR
-; PROD* Low ISR Low ISR
-; FSR0 Low ISR Low ISR
-; PCLATU Always set to 0 Not used
-; PCLATH Low ISR Not used
-; t_dolocal Low ISR High ISR
-; FSR1 Low ISR High ISR (detect[1])
-; FSR2 High ISR (nmra) High ISR (detect[1])
+; W Trashed Trashed
+; STATUS Trashed Trashed
+; BSR Not used Not used
+; t,u,v Low ISR Low ISR
+; TBLPTR*,TABLAT Low ISR Low ISR
+; PROD* Low ISR Low ISR
+; FSR0 Low ISR Low ISR
+; PCLATU Always set to 0 Not used
+; PCLATH Low ISR Not used
+; t_dolocal Low ISR High ISR
+; FSR1 Low ISR High ISR (detect[1])
+; FSR2 High ISR (nmra[1]) High ISR (detect[1])
+; PORTB Special read handling[2] Used normally
+;
+; Main loop detection scan detection scan
+; High ISR NMRA output I2C service
+; Low ISRs everything else everything else
;
; Trashed May be trashed by any routine anywhere. Saved
; during every ISR entry/exit.
; detect_slave_init. Likewise FSR2 is reserved exclusively
; for the NMRA output ISR after nmra_init.
;
+; [2] On the master PIC we the interrupt-on-change feature of PORTB.
+; This means that routines mustn't casually read PORTB. Instead,
+; they should call portb_read from serout.asm.
+;
; General-purpose hardware allocation:
;
; Master Slave
; Timer 0 nmra Disabled
-; Timer 2 tick: 10ms, int. low -
+; Timer 2 tick, int. low -
; Timer 1 - -
; CCP1 - -
; Timer 3 point fire timer point fire timer
;
; <something>_intrl Low ISR service routine.
; Checks for any relevant interrupt.
-; If not, just returns.
+; If not, just returns
; If found, services it and then does either
; intrl_handled or intrl_handled_nostack
; neither of which return; the latter is
-; faster but implies a promise
+; faster but implies a promise
;
;----------------------------------------------------------------------
; MACROS
+@ macro
+ endm
+
+;----------------------------------------
+; For adding a byte to the debug buffer.
+; Not for use in High ISR. In all cases:
+;
+; STATUS any trashed
+; all others any preserved
+
+ ifdef DEBUG
+;----------
+Dv macro ; sorry, but assembler's dw directive isn't case-sensitive
+;
+; W message byte preserved
+;
+ call debugbyte
+ endm
+
+;----------
+Dl macro debug_literal_value
+;
+; W any literal value as specified
+;
+ mov_lw debug_literal_value
+ Dv
+ endm
+
+;----------
+Df macro debug_register_file_address
+;
+; W any value from specified memory location
+;
+ mov_fw debug_register_file_address
+ Dv
+ endm
+ else
+Dv macro
+ endm
+Dl macro debug_literal_value
+ endm
+Df macro debug_register_file_address
+ endm
+ endif
+
;----------------------------------------
; For entering and leaving Low ISR, saving and restoring STATUS and W
; See above under <something>_intrl, and {master,slave}_interrupt_low
endm
;----------------------------------------
-; For setting up TBLPTR according to the picno
+; For setting up TBLPTR
+
+load_tblptr macro value
+;
+; Before After
+; TBLPTR* any set
+; W, STATUS any undefined
+;
+ mov_lw value & 0xff
+ mov_wf TBLPTRL
+
+ mov_lw value >> 8
+ mov_wf TBLPTRH
+
+ if value > 0xffff
+ mov_lw value >> 16
+ mov_wf TBLPTRU
+ else
+ clr_f TBLPTRU
+ endif
+ endm
load_perpic_tblptr macro flash_map_base, perpic_entry_size
;
; and <port> is 0 1 2 3 4 5 6 7. Generally p<picno>_<subsystem>_<pin>
; are equ'd for this.
- radix hex
+ radix hex
p0_cdu_enable equ 5b
p0_rs232_fcin equ 4b
p0_booster_shutdown equ 2b
p0_spare0 equ 0a
p0_booster_dirn equ 0c
p0_booster_pwm equ 1c
- radix dec
+ radix dec
;
; LAT* may be subject to read-modify-write, see below
bc_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4
endm
+pin_znz macro pinspec
+ btg_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4
+ endm
+
pin_vh macro pinspec
bs_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
endm
bc_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
endm
+pin_vhl macro pinspec
+ btg_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
+ endm
+
pin_h macro pinspec
pin_vh pinspec
pin_nz pinspec
bt_f_if0 PORTA + (PORTB-PORTA)*((pinspec-0xa) & 15), pinspec >> 4
endm
+pinlat_ifh macro pinspec
+ bt_f_if1 LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
+ endm
+
+pinlat_ifl macro pinspec
+ bt_f_if0 LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
+ endm
+
+pin_inw_ifh macro pinspec
+ bt_w_if1 pinspec >> 4
+ endm
+
+pin_inw_ifl macro pinspec
+ bt_w_if0 pinspec >> 4
+ endm
+
;----------------------------------------------------------------------
~ijackson / trains.git / blobdiff