;====================================================================== ; common.inc ; common macros & equs etc. ; generally include this at the top of each file. ;---------------------------------------------------------------------- ; COMMON INCLUDES and BOILERPLATE include /usr/share/gputils/header/p18f458.inc radix dec include panic.inc include morse+auto.inc include ../iwjpictest/insn-aliases.inc clock equ -1 include ../iwjpictest/clockvaries.inc include variables+vars.inc include pindata.inc ;---------------------------------------------------------------------- ; Common conventions for function register notation: ; Master Slave ; Registers etc. ; W Trashed Trashed ; STATUS Trashed Trashed ; BSR Not used Not used ; t Low ISR Low ISR ; TBLPTR*,TABLAT Low ISR Low ISR ; FSR0 Low ISR Low ISR ; FSR1 Low ISR High ISR (detect[1]) ; FSR2 Low ISR High ISR (detect[1]) ; ; Trashed May be trashed by any routine anywhere. Saved ; during every ISR entry/exit. ; ; Low ISR May be used/traashed by any routine run in low-priority ; interrupt, or any routine run during initialisation. ; May therefore not be used in background loop with ; interrupts enabled. May not be used by high-priority ; ISR (unless explicitly saved). ; ; High ISR May be used/trashed by any routine run in high-priority ; interrupt, or any routine run during initialisation. ; May therefore not be used elsewhere with interrupts ; enabled. ; ; Only the routines specially noted as intended to ; be called from the High ISR are safe. ; ; ... (subsystem) ; Register is reserved for use by this subsystem, which ; is allowed to expect the value to be preserved. ; Anything else which uses it must save and restore (and ; may also need to disable interrupts, depending on its ; relative status). ; ; Not High May be used by any routine not running in high-priority ; interrupt. Not saved by high-priority interrupt ; entry/exit, so any high-priority interrupt routine which ; uses this register must save and restore it. ; ; A routine which is allowed to trash a register may document that it ; saves that register for the benefit of its callers. ; ; [1] FSR1 and FSR2 on slave pics are reserved exclusively for the ; I2C response and detection code (detect.asm), after det_slave_init. ; ; General-purpose hardware allocation: ; ; Master Slave ; Timer 0 nmra Disabled ; Timer 2 - - ; Timer 1 1ms tick, int. low 1ms tick, int. low ; CCP1 1ms tick, int. low 1ms tick, int. low ; Timer 3 point fire timer point fire timer ; ECCP - - ;---------------------------------------------------------------------- ; MACROS enter_interrupt_low macro mov_ff STATUS, isr_low_save_status mov_wf isr_low_save_w endm return_interrupt_low macro mov_fw isr_low_save_w mov_ff isr_low_save_status, STATUS retfie endm mask_int_high macro bc_f INTCON,GIEH endm unmask_int_high macro bs_f INTCON,GIEH endm tblrd_postinc_fixup macro tblrd *+ dw 0xffff endm tblrd_postdec_fixup macro tblrd *- dw 0xffff endm ;---------------------------------------------------------------------- ; PINSPECS stuff ; ; A PINSPEC is a constant 0x where is a b c d e ; and is 0 1 2 3 4 5 6 7. Generally p__ ; are equ'd for this. radix hex p0_cdu_enable equ 5b p0_rs232_fcin equ 4b p0_booster_shutdown equ 2b p0_booster_overload equ 1b p0_booster_userfault equ 0b p0_spare2 equ 6d p0_spare1 equ 5d p0_rs232_fcout equ 5c pall_perpicled equ 2d pall_pt0reverse equ 7b p0_spare0 equ 0a p0_booster_dirn equ 0c p0_booster_pwm equ 1c radix dec pin_z macro pinspec bs_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4 endm pin_nz macro pinspec bc_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4 endm pin_vh macro pinspec bs_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4 endm pin_vl macro pinspec bc_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4 endm pin_h macro pinspec pin_vh pinspec pin_nz pinspec endm pin_l macro pinspec pin_vl pinspec pin_nz pinspec endm pin_ifh macro pinspec bt_f_if1 PORTA + (PORTB-PORTA)*((pinspec-0xa) & 15), pinspec >> 4 endm pin_ifl macro pinspec bt_f_if0 PORTA + (PORTB-PORTA)*((pinspec-0xa) & 15), pinspec >> 4 endm ;----------------------------------------------------------------------