1 ;======================================================================
4 ; This file implements panic_routine, which is called by the
5 ; `panic' macro in panic.inc. See panic.inc for the functionality
10 ;---------------------------------------------------------------------------
11 ; reserved access bank locations
19 panicst_restart_i2c equ 7
21 panicst_ferroerr equ 4
22 panicst_writeslave equ 3
26 panic_vars_section udata 0x060 + maxpics ; not available via access bank
27 ; used in panic routine for temporary storage:
31 register_counter res 1
34 panic_address res 1 ; condensed form of message start addr.
35 panic_morse res 1 ; # bytes of morse msg in panic readout
36 panic_regs res 1 ; # registers in panic readout
51 panic_stack res stack_depth*3
53 ;****************************************************************************
57 ;****************************************************************************
61 ; switch off interrupts and power
62 ; reconfigure timer0 for writing diagnostic msg to the LED
64 mov_ff INTCON, psave_intcon
65 bc_f INTCON, GIEH ; disable all interrupts
70 mov_ff LATC, psave_latc
72 ; now we have time to save registers etc
73 ; (turning off interrupts is urgent (we might get interrupted while
74 ; panicing which would be bad because we might forget to panic).
79 mov_ff TABLAT, psave_tablat
80 mov_ff TBLPTRL, psave_tblptr
81 mov_ff TBLPTRH, psave_tblptr+1
82 mov_ff TBLPTRU, psave_tblptr+2
83 mov_ff FSR0L, psave_fsr0
84 mov_ff FSR0H, psave_fsr0+1
85 mov_ff FSR1L, psave_fsr1
86 mov_ff FSR1H, psave_fsr1+1
87 mov_ff PRODL, psave_prod
88 mov_ff PRODH, psave_prod+1
89 mov_ff STKPTR, psave_stkptr
91 mov_lfsr panic_stack + stack_depth*3 - 1, 0
101 clr_f STKPTR ; avoids stack overruns
106 ; re-initialise timer0 config, etc.
108 bra_z panic_setup_if_master
110 morse_t0setup sclock, (1<<TMR0ON), t0l_count, t0h_count
111 bra panic_setup_endif_masterslave
113 panic_setup_if_master
116 call serial_write_char
117 morse_t0setup mclock, (1<<TMR0ON), t0l_count, t0h_count
118 panic_setup_endif_masterslave
120 ; get # bytes of morse msg, # registers in panic readout, message start addr.
121 ; back from condensed message start addr. stored in panic_address
124 mov_lw 4 ; size of each message's details
128 add_lw (morse_messages_start)/256
132 tblrd *+ ; read 1st byte of error message
133 ; (gives # bytes morse, # bytes registers)
134 dw 0xffff ; silicon errata: B4 issue 4
136 mov_ff TABLAT,panic_morse
138 and_wff panic_morse ; panic_morse now contains # bytes of morse msgs
140 mov_ff TABLAT,panic_regs
143 swap_f panic_regs ; panic_regs now contains # registers to read
147 rcall morsemsg ; transmit morse in red
151 rcall registermsg ; transmit contents of registers in
152 ; red(=low) and blue(=high)
156 ;****************************************************************************
160 ; wrapper round morse_readout to flash the per-pic led red for a morse msg
163 clr_f morse_counter ; clear loop counter
167 cmp_fw_ifge morse_counter ; if loop counter >=panic_morse
168 return ; return to panic
171 mov_ff TABLAT,flash_pattern
177 ;--------------------------
180 ; Flashes the per-pic led and black in a specified pattern.
182 ; The pattern is specified as the state for 8 identically-long time
183 ; periods each as long as a morse `dot', encoded into a byte with
184 ; most significant bit first.
187 ; flash_pattern flash pattern preserved
188 ; bit_counter any undefined
195 dec_f_ifz bit_counter ; done all the bits yet ?
199 rl_f flash_pattern ; top bit goes into N,
201 bra_n morse_readout_if_led_1
203 morse_readout_if_led_0
205 bra morse_readout_endif_led
207 morse_readout_if_led_1
210 morse_readout_endif_led
212 bra morse_readout_loop
214 ;--------------------------
215 ;--------------------------
219 clr_f register_counter ; clear loop counter
223 cmp_fw_ifge register_counter ; if loop counter >=panic_regs
224 return ; return to panic
228 mov_fw TABLAT ; TABLAT has the 8-bit version
229 mov_wf FSR0L ; of the address. So, 8 bits
230 ; go straight into FSR0L.
232 mov_lw 0x0f ; For FSR0H, we see if the
233 mov_fw FSR0H ; address XX is >=0x60.
234 ; If it is then we meant 0xfXX;
235 mov_lw 0x5f ; if not then we meant 0x0XX.
236 cmp_fw_ifle FSR0L ; (This is just like PIC does
237 clr_f FSR0H ; for insns using Access Bank)
239 mov_ff INDF0,flash_pattern
240 rcall register_readout
242 inc_f register_counter ;increment loop counter
247 ;--------------------------
251 ; Flashes the per-pic led red(0) and green(1) in a specified pattern.
252 ; (black gap between each bit)
254 ; The pattern is specified as the state for 8 identically-long time
255 ; periods each as long as a morse `dot', encoded into a byte with
256 ; most significant bit first.
259 ; flash_pattern flash pattern preserved
260 ; bit_counter any undefined
262 clr_f bit_counter ; clear loop counter
266 register_readout_loop
268 cmp_fw_ifge bit_counter ; if loop counter >=8 (register
273 cmp_fw_ifne bit_counter ; if loop counter !=4 (nybble length),
274 ; skip insertion of extra black space
275 bra not_nybble_boundary
279 rl_f flash_pattern ; top bit goes into N flag,
281 bra_n register_readout_if_led_1
283 register_readout_if_led_0
285 bra register_readout_endif_led
287 register_readout_if_led_1
290 register_readout_endif_led
291 inc_f bit_counter ; increment loop counter
295 bra register_readout_loop
298 ;****************************************************************************
299 ; GENERAL SUBROUTINES
301 ;----------------------------------------
302 waiting16 rcall waiting8
303 waiting8 rcall waiting4
304 waiting4 rcall waiting2
305 waiting2 rcall waiting
307 ; waits for a fixed interval, depending on the configuration of TMR0
309 bc_f INTCON,2 ; clear timer0 interrupt bit (p109)
310 ; Interrupt happens on overflow. So start at 65535-morse_t0cycles:
312 mov_wf TMR0H ; p107 set high byte of timer0 (buffered,
313 ; only actually set when write to tmr0l occurs)
315 mov_wf TMR0L ; set timer0 low byte - timer now set
316 waiting_loop ; wait for timer0 interrupt, or some other interrupt
317 bt_f_if1 INTCON,TMR0IF
320 bt_f_if1 idloc1, idloc1_master
324 bt_f_if0 SSPCON1, SSPEN
325 bra waiting_loop ; no readouts if i2c is disabled
326 ; slave, i2c enabled:
329 call pan_i2cs_interrupt
333 ;----------------------------------------
334 ; MASTER'S PANIC SERIAL PORT HANDLING
336 ;--------------------
338 bt_f_if1 PIR1,RCIF ; host sent us something ?
341 bt_f_if0 SSPCON1, SSPEN
343 ; master, i2c enabled:
346 rcall pan_i2cm_interrupt
353 bra_nz panicd_serialrx_err_loop
354 ; yay! host ack'd ferr/oerr
355 bc_f panicst, panicst_ferroerr
356 return ; return from panicd_serialrx
360 bs_f panicst, panicst_ferroerr
362 bc_f RCSTA, RCEN ; disable } to clear FERR/OERR
363 mov_fw RCREG ; read RCREG } (see PIC18FXX8 DS p182)
364 bs_f RCSTA, RCEN ; reenable }
365 panicd_serialrx_err_loop
366 bt_f_if0 PIR1, RCIF ; wait for a byte 0x01 to ack the overrun/error
367 bra panicd_serialrx_err_loop
372 bra panicd_serialrx_err
374 bra panicd_serialrx_err
375 bt_f_if1 panicst, panicst_ferroerr
380 ;****************************************************************************
385 panicd_process_input_byte
386 ; W instruction from host or master
389 ; we've received 0x00:
392 bs_f panicst, panicst_acked
397 bt_f_if0 panicst, panicst_acked ; well, ignore that !
399 ; OK, we have an instruction:
402 bra write_if_setbytetowrite
404 bra panic_crashread_setpointer
405 bt_f_if0 idloc1,idloc1_master
406 return ; all the remaining options are for master only
408 bra write_if_master_slaveselect
410 bra write_if_master_masterread
411 bra write_if_master_slaveread
415 panic_crashread_setpointer
416 ; W byte from master or host undefined
417 ; FSR1* crashread pointer updated
418 ; t, STATUS, PROD* any undefined
419 ; all others any preserved
430 ;======================================================================
431 ; MASTER READOUT AND MASTER READOUT OF SLAVES
434 write_if_setbytetowrite
435 bt_f_if0 idloc1,idloc1_master
436 return ; for master only
439 mov_wf panic_valcount
440 bs_f panicst, panicst_writeslave
444 write_if_master_slaveread
445 mov_wf panic_valcount
446 bc_f panicst, panicst_writeslave
450 write_if_master_slaveselect
452 bt_f_if1 panicst, panicst_writeslave
453 bra pan_i2cm_write_start
454 bra pan_i2cm_read_start
457 write_if_master_masterread
459 mov_wf panic_valcount
460 write_if_master_masterread_loop
462 call serial_write_char
463 dec_f_ifnz panic_valcount
464 bra write_if_master_masterread_loop
468 pan_i2cmu_read_got_byte
469 call serial_write_char
470 dec_fw_ifnz panic_valcount
471 bra pan_i2cm_read_another
475 pan_i2cmu_write_next_byte
476 mov_fw panic_valcount
478 bt_f_if1 panicst, panicst_writeslave
480 bc_f panicst, panicst_writeslave
486 goto serial_write_char
488 ;======================================================================
493 pan_i2csu_write_begin
498 mov_lw 0x80 ; M0000000
499 bt_f_if0 panicst, panicst_acked
507 pan_i2csu_read_another
508 bt_f_if1 panicst, panicst_acked
509 bra i2csu_read_panicd_ok
519 near_serialrx_table code 0x2100
522 panic_crashread_commanded
523 bs_f panicst, panicst_acked ; since we were asked to
526 ;***************************************************************************