1 ;======================================================================
4 ; This file implements panic_routine, which is called by the
5 ; `panic' macro in panic.inc. See panic.inc for the functionality
10 ;---------------------------------------------------------------------------
11 ; reserved access bank locations
19 panicst_restart_i2c equ 7
21 panicst_ferroerr equ 4
22 panicst_writeslave equ 3
26 panic_vars_section udata 0x060 + maxpics ; not available via access bank
27 ; used in panic routine for temporary storage:
31 register_counter res 1
34 panic_address res 1 ; condensed form of message start addr.
35 panic_morse res 1 ; # bytes of morse msg in panic readout
36 panic_regs res 1 ; # registers in panic readout
51 panic_stack res stack_depth*3
53 ;****************************************************************************
57 ;****************************************************************************
61 ; switch off interrupts and power
62 ; reconfigure timer0 for writing diagnostic msg to the LED
64 mov_ff INTCON, psave_intcon
65 bc_f INTCON, GIEH ; disable all interrupts
70 mov_ff LATC, psave_latc
72 ; now we have time to save registers etc
73 ; (turning off interrupts is urgent (we might get interrupted while
74 ; panicing which would be bad because we might forget to panic).
79 mov_ff TABLAT, psave_tablat
80 mov_ff TBLPTRL, psave_tblptr
81 mov_ff TBLPTRH, psave_tblptr+1
82 mov_ff TBLPTRU, psave_tblptr+2
83 mov_ff FSR0L, psave_fsr0
84 mov_ff FSR0H, psave_fsr0+1
85 mov_ff FSR1L, psave_fsr1
86 mov_ff FSR1H, psave_fsr1+1
87 mov_ff PRODL, psave_prod
88 mov_ff PRODH, psave_prod+1
89 mov_ff STKPTR, psave_stkptr
91 mov_lfsr panic_stack + stack_depth*3 - 1, 0
101 clr_f STKPTR ; avoids stack overruns
106 ; re-initialise timer0 config, etc.
108 bra_z panic_setup_if_master
110 morse_t0setup sclock, (1<<TMR0ON), t0l_count, t0h_count
111 bra panic_setup_endif_masterslave
113 panic_setup_if_master
114 pin_l p0_booster_userfault
117 call serial_write_char
118 morse_t0setup mclock, (1<<TMR0ON), t0l_count, t0h_count
119 panic_setup_endif_masterslave
121 ; get # bytes of morse msg, # registers in panic readout, message start addr.
122 ; back from condensed message start addr. stored in panic_address
125 mov_lw 4 ; size of each message's details
129 add_lw (morse_messages_start)/256
133 tblrd *+ ; read 1st byte of error message
134 ; (gives # bytes morse, # bytes registers)
135 dw 0xffff ; silicon errata: B4 issue 4
137 mov_ff TABLAT,panic_morse
139 and_wff panic_morse ; panic_morse now contains # bytes of morse msgs
141 mov_ff TABLAT,panic_regs
144 swap_f panic_regs ; panic_regs now contains # registers to read
148 rcall morsemsg ; transmit morse in red
152 rcall registermsg ; transmit contents of registers in
153 ; red(=low) and blue(=high)
157 ;****************************************************************************
161 ; wrapper round morse_readout to flash the per-pic led red for a morse msg
164 clr_f morse_counter ; clear loop counter
168 cmp_fw_ifge morse_counter ; if loop counter >=panic_morse
169 return ; return to panic
172 mov_ff TABLAT,flash_pattern
178 ;--------------------------
181 ; Flashes the per-pic led and black in a specified pattern.
183 ; The pattern is specified as the state for 8 identically-long time
184 ; periods each as long as a morse `dot', encoded into a byte with
185 ; most significant bit first.
188 ; flash_pattern flash pattern preserved
189 ; bit_counter any undefined
196 dec_f_ifz bit_counter ; done all the bits yet ?
200 rl_f flash_pattern ; top bit goes into N,
202 bra_n morse_readout_if_led_1
204 morse_readout_if_led_0
206 bra morse_readout_endif_led
208 morse_readout_if_led_1
211 morse_readout_endif_led
213 bra morse_readout_loop
215 ;--------------------------
216 ;--------------------------
220 clr_f register_counter ; clear loop counter
224 cmp_fw_ifge register_counter ; if loop counter >=panic_regs
225 return ; return to panic
229 mov_fw TABLAT ; TABLAT has the 8-bit version
230 mov_wf FSR0L ; of the address. So, 8 bits
231 ; go straight into FSR0L.
233 mov_lw 0x0f ; For FSR0H, we see if the
234 mov_fw FSR0H ; address XX is >=0x60.
235 ; If it is then we meant 0xfXX;
236 mov_lw 0x5f ; if not then we meant 0x0XX.
237 cmp_fw_ifle FSR0L ; (This is just like PIC does
238 clr_f FSR0H ; for insns using Access Bank)
240 mov_ff INDF0,flash_pattern
241 rcall register_readout
243 inc_f register_counter ;increment loop counter
248 ;--------------------------
252 ; Flashes the per-pic led red(0) and green(1) in a specified pattern.
253 ; (black gap between each bit)
255 ; The pattern is specified as the state for 8 identically-long time
256 ; periods each as long as a morse `dot', encoded into a byte with
257 ; most significant bit first.
260 ; flash_pattern flash pattern preserved
261 ; bit_counter any undefined
263 clr_f bit_counter ; clear loop counter
267 register_readout_loop
269 cmp_fw_ifge bit_counter ; if loop counter >=8 (register
274 cmp_fw_ifne bit_counter ; if loop counter !=4 (nybble length),
275 ; skip insertion of extra black space
276 bra not_nybble_boundary
280 rl_f flash_pattern ; top bit goes into N flag,
282 bra_n register_readout_if_led_1
284 register_readout_if_led_0
286 bra register_readout_endif_led
288 register_readout_if_led_1
291 register_readout_endif_led
292 inc_f bit_counter ; increment loop counter
296 bra register_readout_loop
299 ;****************************************************************************
300 ; GENERAL SUBROUTINES
302 ;----------------------------------------
303 waiting16 rcall waiting8
304 waiting8 rcall waiting4
305 waiting4 rcall waiting2
306 waiting2 rcall waiting
308 ; waits for a fixed interval, depending on the configuration of TMR0
310 bt_f_if1 idloc1,idloc1_master
311 pin_z p0_booster_userfault
313 bc_f INTCON,2 ; clear timer0 interrupt bit (p109)
314 ; Interrupt happens on overflow. So start at 65535-morse_t0cycles:
316 mov_wf TMR0H ; p107 set high byte of timer0 (buffered,
317 ; only actually set when write to tmr0l occurs)
319 mov_wf TMR0L ; set timer0 low byte - timer now set
320 waiting_loop ; wait for timer0 interrupt, or some other interrupt
321 bt_f_if1 INTCON,TMR0IF
324 bt_f_if1 idloc1, idloc1_master
328 bt_f_if0 SSPCON1, SSPEN
329 bra waiting_loop ; no readouts if i2c is disabled
330 ; slave, i2c enabled:
333 call pan_i2cs_interrupt
337 ;----------------------------------------
338 ; MASTER'S PANIC SERIAL PORT HANDLING
340 ;--------------------
342 bt_f_if1 PIR1,RCIF ; host sent us something ?
345 bt_f_if0 SSPCON1, SSPEN
347 ; master, i2c enabled:
350 rcall pan_i2cm_interrupt
357 bra_nz panicd_serialrx_err_loop
358 ; yay! host ack'd ferr/oerr
359 bc_f panicst, panicst_ferroerr
360 return ; return from panicd_serialrx
364 bs_f panicst, panicst_ferroerr
365 bc_f RCSTA, RCEN ; disable } to clear FERR/OERR
366 mov_fw RCREG ; read RCREG } (see PIC18FXX8 DS p182)
367 bs_f RCSTA, RCEN ; reenable }
368 panicd_serialrx_err_loop
369 bt_f_if0 PIR1, RCIF ; wait for a byte 0x01 to ack the overrun/error
370 bra panicd_serialrx_err_loop
374 pin_nz p0_booster_userfault
376 bra panicd_serialrx_err
378 bra panicd_serialrx_err
379 bt_f_if1 panicst, panicst_ferroerr
384 ;****************************************************************************
389 panicd_process_input_byte
390 ; W instruction from host or master
393 ; we've received 0x00:
396 bs_f panicst, panicst_acked
401 bt_f_if0 panicst, panicst_acked ; well, ignore that !
403 ; OK, we have an instruction:
406 bra write_if_setbytetowrite
408 bra panic_crashread_setpointer
409 bt_f_if0 idloc1,idloc1_master
410 return ; all the remaining options are for master only
412 bra write_if_master_slaveselect
414 bra write_if_master_masterread
415 bra write_if_master_slaveread
419 panic_crashread_setpointer
420 ; W byte from master or host undefined
421 ; FSR1* crashread pointer updated
422 ; t, STATUS, PROD* any undefined
423 ; all others any preserved
434 ;======================================================================
435 ; MASTER READOUT AND MASTER READOUT OF SLAVES
438 write_if_setbytetowrite
439 bt_f_if0 idloc1,idloc1_master
440 return ; for master only
443 mov_wf panic_valcount
444 bs_f panicst, panicst_writeslave
448 write_if_master_slaveread
449 mov_wf panic_valcount
450 bc_f panicst, panicst_writeslave
454 write_if_master_slaveselect
456 bt_f_if1 panicst, panicst_writeslave
457 bra pan_i2cm_write_start
458 bra pan_i2cm_read_start
461 write_if_master_masterread
463 mov_wf panic_valcount
464 write_if_master_masterread_loop
466 call serial_write_char
467 dec_f_ifnz panic_valcount
468 bra write_if_master_masterread_loop
472 pan_i2cmu_read_got_byte
473 call serial_write_char
474 dec_fw_ifnz panic_valcount
475 bra pan_i2cm_read_another
479 pan_i2cmu_write_next_byte
480 mov_fw panic_valcount
482 bt_f_if1 panicst, panicst_writeslave
484 bc_f panicst, panicst_writeslave
490 goto serial_write_char
492 ;======================================================================
497 pan_i2csu_write_begin
502 mov_lw 0x80 ; M0000000
503 bt_f_if0 panicst, panicst_acked
511 pan_i2csu_read_another
512 bt_f_if1 panicst, panicst_acked
513 bra i2csu_read_panicd_ok
523 near_serialrx_table code 0x2100
526 panic_crashread_commanded
527 bs_f panicst, panicst_acked ; since we were asked to
530 ;***************************************************************************