1 ;######################################################################
2 ; i2clib.inc - I2C LIBRARY - IMPLEMENTATION
4 ; See i2clib.asm for documentation of the interface to this file.
6 include /usr/share/gputils/header/p18f458.inc
8 include ../iwjpictest/insn-aliases.inc
10 include morse+auto.inc
12 ;======================================================================
17 ; m_... routines used by master only
18 ; s_... routines used by slave only
19 ; <any other name> routines used by both
21 ; [ms]_event_... event handler, branched to from interrupt
22 ; handler; conditions are as in the name;
23 ; should `return' at end which will return
24 ; from i2c[ms]_interrupt
26 ; [sm]_event_bad[_...] event handler which panics; called when i2c
27 ; controller did something unexpected
29 ; m_improper_... panics; called when main program
30 ; does something wrong
32 ; [ms]_<anything else> routines or labels of some other kind
34 ; Whenever flow does not pass past the end of some code, we
35 ; have a boundary `;----------', and when flow passes past
36 ; an important label we sometimes mark it specially with `;...',
41 ; bt_f_if0 st, st_something
45 ; m_event_several_including_spong
46 ; bs_f st, st_sponging
47 ; bra metasyntacticing
52 ;============================================================
53 ; COMMON ADMINISTRATIVE ROUTINES and VARIABLES
59 sspcon2 res 1 ; master only
60 slave res 1 ; master only
64 ; st is a bitmask, bit set in visible states:
66 st_starting equ 7 ; Writing-Setup?,Reading-Busy?
67 st_addressing equ 6 ; Writing-Setup?,Reading-Busy?
68 st_writing equ 5 ; Writing-* [Idle-going-]Receiving
69 st_subsequent equ 4 ; Writing? Receiving
70 st_reading equ 3 ; Reading-* Transmitting
71 st_awaiting equ 2 ; Reading-Wait
72 st_acking equ 1 ; Reading-Busy?,Stopping(from read)
73 st_stopping equ 0 ; Stopping
74 ; ...? means not always set in that state
80 ; computes slave address in form suitable for use in i2c controller
81 ; actual i2c slave address is (slave number) + 0b0001000
82 ; W slave number i2c address * 2
87 ;======================================================================
92 mov_lw 100-1 ; baud rate = Fosc/(4*(SSPADD+1))
93 mov_wf SSPADD ; Fosc=20MHz, so SSPADD==99 means 50kbit/s
94 mov_lw 0x08 ; !SSPEN, Master mode
96 clr_f SSPCON2 ; nothing going
97 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
104 ; We have an interrupt:
106 mov_ff SSPSTAT, sspstat
107 mov_ff SSPCON1, sspcon1
108 mov_ff SSPCON2, sspcon2
110 bt_f_if1 sspcon1, WCOL
112 bt_f_if1 sspcon1, SSPOV
115 ; No ? Well, then the I2C should be idle now:
117 and_lw ~0x60 ; ACKSTAT,ACKDT
121 bt_f_if1 sspstat, R_W
124 bt_f_if1 st, st_stopping
125 bra m_event_done_stopping
127 bt_f_if1 st, st_starting
128 bra m_event_done_starting
131 bt_f_if1 st, st_addressing
132 bra m_event_done_addressing
134 bt_f_if1 st, st_writing
135 bra m_event_done_writing
137 bt_f_if1 st, st_acking
138 bra m_event_done_acking
140 bt_f_if1 st, st_reading
141 bra m_event_done_reading
146 ;========================================
147 ; MASTER - STARTING, ADDRESSING, STOPPING
151 ; st checked for busyness correct
152 ; st_reading/writing set unchanged
153 ; st_starting clear set
155 ; slave any slave_number
156 ; expects to return directly to main program (caller)
159 bra_nz m_improper_slave
165 m_event_done_starting
169 bt_f_if1 st, st_reading
170 bs_w 0 ; address bottom bit means read
174 bs_f st, st_addressing
178 m_event_done_addressing
179 bt_f_if1 sspcon2, ACKSTAT
180 bra m_bad_address_ack
183 bc_f st, st_addressing
184 bt_f_if1 st, st_reading
185 bra m_event_done_addressing_read
186 bra m_event_done_addressing_write
190 ; st_stopping clear set
191 ; st_reading/acking/writing any unchanged
192 ; expects to return directly to main program or to end interrupt handler
198 m_event_done_stopping
211 ;========================================
217 ; State Idle Writing-Setup
220 bra m_improper_write_start
227 ; Did slave ack our byte ? It had better have done !
228 bt_f_if1 sspcon2, ACKSTAT
231 bs_f st, st_subsequent
234 m_event_done_addressing_write
236 ; st_addressing cleared
237 call i2cmu_write_next_byte
238 bra_z m_event_write_mustfinish
239 ; OK, we have the next byte:
245 m_event_write_mustfinish
246 bt_f_if0 st, st_subsequent
247 bra m_improper_write_finish
252 m_improper_write_start
256 m_improper_write_finish
259 ;========================================
265 ; State Idle Reading-Busy
268 bra m_improper_read_start
274 m_event_done_addressing_read
275 m_event_done_acking_readmore
277 ; st_addressing/acking cleared
289 goto i2cmu_read_got_byte
293 ; State Reading-Wait Reading-Busy
294 bt_f_if0 st, st_awaiting
295 bra m_improper_read_another
296 ; OK, we're fine to read another:
300 ; st_reading 1 iff not done unchanged
301 ; st_awaiting still set cleared
302 ; st_acking clear set
303 ; expects to return directly to main program or to end interrupt handler
306 bc_f SSPCON2, ACKDT ; ACKDT=0 means to acknowledge
312 ; State Reading-Wait Stopping
315 bt_f_if0 st, st_awaiting
316 bra m_improper_read_done
325 bt_f_if1 st, st_reading
326 bra m_event_done_acking_readmore
331 m_improper_read_start
335 m_improper_read_another
342 ;======================================================================
347 ; W slave number undefined
351 mov_lw 0x16 ; !SSPEN, CKP(release), I2C 7-bit slave no-SP-int
353 mov_lw 0x01 ; !GCEN, SEN
355 mov_lw 0x8 ; SMP(noslew), !CKE(!smbus)
358 ; Actually engages the I2C controller, which must already have
359 ; been set up (all but SSPEN):
360 ; SSPADD,SSPCON1,SSPCON2 configured correctly unchanged
361 ; SSPSTAT configured correctly unchanged, except:
362 ; SSPSTAT<SSPEN> 0 (disabled) 1 (enabled)
363 ; SSPIE 0 (disabled) 1 (enabled)
364 ; TRISB<1,0> any configured for I2C
365 ; SSPIP any configured correctly
366 ; GIEL 0 (disabled) 0 (disabled)
367 ; ssp* shadows any all bits set
378 ;========================================
379 ; SLAVE - INTERRUPT HANDLING
381 ; In general, we figure out our state and then see what kind of events
382 ; we were expecting. Bits we want to check:
383 ; 80 60 20 10 08 04 02 01
384 ; SMP CKE D_A P S R_W UA BF
385 ; set clr data? stop start read? clr full?
386 ; (we don't usually mention SMP, CKE and UA below)
390 chkvals_start_sspstat macro
394 chkval macro lastval, value, label
395 xor_lw value ^ lastval
399 chkvals_addrrecv macro lastval
400 chkval lastval, 0x8c, s_event_idle_addrrecvread ; A,!P, S,R,!BF
401 chkval 0x8c, 0x89, s_event_idle_addrrecvwrite ; A,!P, S,W,BF
403 chkvals_addrrecv_lastval equ 0x89
409 ; We have an interrupt:
411 bt_f_if1 sspcon1, WCOL
413 bt_f_if1 sspcon1, SSPOV
416 ; Firstly, clear the interrupt flag so that if something else happens
417 ; while we faff, the interrupt will be regenerated:
420 mov_ff SSPSTAT, sspstat
421 mov_ff SSPCON1, sspcon1
423 bt_f_if0 st, st_reading
426 bt_f_if0 st, st_writing
430 chkvals_start_sspstat
433 panic morse_SS ; slave, interrupt, controller in bad state
435 ;========================================
439 s_event_idle_addrrecvread
441 call i2csu_read_begin
442 bra s_events_reading_datasend
446 chkvals_start_sspstat
447 chkval 0, 0xac, s_event_reading_datasent ; D,!P, S,R,!BF
449 ; Whatever is happening, we're done reading now !
453 chkvals_start_sspstat
454 chkval 0, 0xa8, s_event_reading_datanack ; D,!P, S,!R,!BF
455 ; Or, maybe it was nack and then we were reselected:
456 chkvals_addrrecv 0xa8
461 s_event_reading_datasent
462 call i2csu_read_another
463 s_events_reading_datasend
466 s_event_reading_datanack
469 ;========================================
473 s_event_idle_addrrecvwrite
474 bs_f SSPCON1, 3 ; we'll need the Stop interrupt
476 ; well, this is all fine so far, so do carry on:
479 ; W any byte from master
480 ; i2c controller waiting due to SEN etc continuing with next byte
487 chkvals_start_sspstat
488 chkval 0, 0xa9, s_event_writing_datarecv ; D,!P, S,W,BF
490 ; Well, we're done writing now in any case
492 bc_f SSPCON1, 3 ; no Start and Stop interrupts any more
493 call i2csu_write_done
495 ; Who knows what might have happened. We may have
496 ; missed a number of S and P due to delay between
497 ; clearing SSPIF and SSPM3(s&p-intrs) so we can't be
500 ; First, the nice cases:
501 chkvals_start_sspstat
506 and_lw 0xc7 ; ?D_A, ?P; ?S
507 xor_lw 0x80 ; SMP, !CKE, !R_W, !UA, !BF
515 s_event_writing_datarecv
516 rcall s_write_slurpbyte
518 bt_f_if1 st, st_subsequent
519 goto i2csu_write_another
520 ; not subsequent (yet):
522 bs_f st, st_subsequent
523 goto i2csu_write_begin
525 ;======================================================================