1 ;######################################################################
2 ; i2clib.inc - I2C LIBRARY - IMPLEMENTATION
4 ; See i2clib.asm for documentation of the interface to this file.
6 include /usr/share/gputils/header/p18f458.inc
8 include ../iwjpictest/insn-aliases.inc
11 include ../iwjpictest/clockvaries.inc
13 include morse+auto.inc
15 ;======================================================================
20 ; m_... routines used by master only
21 ; s_... routines used by slave only
22 ; <any other name> routines used by both
24 ; [ms]_event_... event handler, branched to from interrupt
25 ; handler; conditions are as in the name;
26 ; should `return' at end which will return
27 ; from i2c[ms]_interrupt
29 ; [sm]_event_bad[_...] event handler which panics; called when i2c
30 ; controller did something unexpected
32 ; m_improper_... panics; called when main program
33 ; does something wrong
35 ; [ms]_<anything else> routines or labels of some other kind
37 ; Whenever flow does not pass past the end of some code, we
38 ; have a boundary `;----------', and when flow passes past
39 ; an important label we sometimes mark it specially with `;...',
44 ; bt_f_if0 st, st_something
48 ; m_event_several_including_spong
49 ; bs_f st, st_sponging
50 ; bra metasyntacticing
55 ;============================================================
56 ; COMMON ADMINISTRATIVE ROUTINES and VARIABLES
62 sspcon2 res 1 ; master only
63 slave res 1 ; master only
64 slave_next res 1 ; master only
69 ; st is a bitmask, bit set in visible states:
71 st_starting equ 7 ; Writing-Setup?,Reading-Busy?
72 st_addressing equ 6 ; Writing-Setup?,Reading-Busy?
73 st_writing equ 5 ; Writing-* [Idle-going-]Receiving
74 st_subsequent equ 4 ; Writing? Receiving
75 st_reading equ 3 ; Reading-* Transmit-*
76 st_awaiting equ 2 ; Reading-Wait Transmit-Wait
77 st_acking equ 1 ; Reading-Busy?,Stopping(from read)
78 st_stopping equ 0 ; Stopping
79 ; ...? means not always set in that state
85 ; computes slave address in form suitable for use in i2c controller
86 ; actual i2c slave address is (slave number) + 0b0001000
87 ; W slave number i2c address * 2
93 improper_read_done_data
96 ;======================================================================
105 mov_lw 0x08 ; !SSPEN, Master mode
107 clr_f SSPCON2 ; nothing going
108 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
116 ; We have an interrupt:
118 mov_ff SSPSTAT, sspstat
119 mov_ff SSPCON1, sspcon1
120 mov_ff SSPCON2, sspcon2
124 mov_lw (1<<WCOL) | (1<<SSPOV)
128 ; No ? Well, then the I2C should be idle now:
130 and_lw ~((1<<ACKSTAT) | (1<<ACKDT)) ; those two are ok if set
134 bt_f_if1 sspstat, R_W
137 bt_f_if1 st, st_stopping
138 bra m_event_done_stopping
140 bt_f_if1 st, st_starting
141 bra m_event_done_starting
144 bt_f_if1 st, st_addressing
145 bra m_event_done_addressing
147 bt_f_if1 st, st_writing
148 bra m_event_done_writing
150 bt_f_if1 st, st_acking
151 bra m_event_done_acking
153 bt_f_if1 st, st_reading
154 bra m_event_done_reading
159 ;========================================
160 ; MASTER - STARTING, ADDRESSING, STOPPING
164 ; st checked for busyness correct
165 ; st_reading/writing set unchanged
166 ; st_starting clear set
168 ; slave any slave_number
169 ; expects to return directly to main program (caller)
171 bra_z m_improper_slave
175 bra_nz m_improper_slave
180 m_event_done_starting
184 bt_f_if1 st, st_reading
185 bs_w 0 ; address bottom bit means read
189 bs_f st, st_addressing
193 m_event_done_addressing
194 bt_f_if1 sspcon2, ACKSTAT
195 bra m_bad_address_ack
198 bc_f st, st_addressing
199 bt_f_if1 st, st_reading
200 bra m_event_done_addressing_read
201 bra m_event_done_addressing_write
205 ; st_stopping clear set
206 ; st_reading/acking/writing any unchanged
207 ; expects to return directly to main program or to end interrupt handler
213 m_event_done_stopping
226 ;========================================
232 ; State Idle Writing-Setup
235 bra m_improper_write_start
242 ; Did slave ack our byte ? It had better have done !
243 bt_f_if1 sspcon2, ACKSTAT
246 bs_f st, st_subsequent
249 m_event_done_addressing_write
251 ; st_addressing cleared
252 call i2cmu_write_next_byte
253 bra_z m_event_write_mustfinish
254 ; OK, we have the next byte:
260 m_event_write_mustfinish
261 bt_f_if0 st, st_subsequent
262 bra m_improper_write_finish
267 m_improper_write_start
271 m_improper_write_finish
274 ;========================================
280 ; State Idle Reading-Busy
283 bra m_read_start_busy
290 bt_f_if1 st, st_awaiting
296 ; Main program would like to address another slave.
298 bra_z m_improper_slave
302 m_event_done_addressing_read
303 m_event_done_acking_readmore
305 ; st_addressing/acking cleared
317 goto i2cmu_read_got_byte
321 ; State Reading-Wait Reading-Busy
322 bt_f_if0 st, st_awaiting
323 bra m_improper_read_another
324 ; OK, we're fine to read another:
328 ; st_reading 1 iff not done unchanged
329 ; st_awaiting still set cleared
330 ; st_acking clear set
331 ; expects to return directly to main program or to end interrupt handler
334 bc_f SSPCON2, ACKDT ; ACKDT=0 means to acknowledge
335 bt_f_if0 st, st_reading
336 bs_f SSPCON2, ACKDT ; don't ack last byte
342 ; State Reading-Wait Stopping
345 bt_f_if0 st, st_awaiting
346 bra improper_read_done_data
355 bt_f_if1 st, st_reading
356 bra m_event_done_acking_readmore
360 ; ok, we want to read another:
365 bra m_start_or_restart
368 m_improper_read_another
371 ;======================================================================
376 ; W slave number undefined
380 mov_lw 0x16 ; !SSPEN, CKP(release), I2C 7-bit slave no-SP-int
382 mov_lw 0x01 ; !GCEN, SEN
384 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
387 ; Actually engages the I2C controller, which must already have
388 ; been set up (all but SSPEN):
389 ; SSPADD,SSPCON1,SSPCON2 configured correctly unchanged
390 ; SSPSTAT configured correctly unchanged, except:
391 ; SSPSTAT<SSPEN> 0 (disabled) 1 (enabled)
392 ; SSPIE 0 (disabled) 1 (enabled)
393 ; TRISB<1,0> any configured for I2C
394 ; SSPIP any configured correctly
395 ; GIEL 0 (disabled) 0 (disabled)
396 ; ssp* shadows any all bits set
408 ;========================================
409 ; SLAVE - INTERRUPT HANDLING
411 ; In general, we figure out our state and then see what kind of events
412 ; we were expecting. Bits we want to check:
413 ; 80 60 20 10 08 04 02 01
414 ; SMP CKE D_A P S R_W UA BF
415 ; set clr data? stop start read? clr full?
416 ; (we don't usually mention SMP, CKE and UA below)
420 chkvals_start macro what
424 chkval macro lastval, value, label
425 xor_lw value ^ lastval
429 chkvals_addrrecv macro lastval
430 chkval lastval, 0x8c, s_event_idle_addrrecvread ; A,!P, S,R,!BF
431 chkval 0x8c, 0x89, s_event_idle_addrrecvwrite ; A,!P, S,W,BF
433 chkvals_addrrecv_lastval equ 0x89
436 i2cs_interrupt ; 4cy interrupt latency + 3cy until branch to here
439 ; We have an interrupt:
441 ; Firstly, clear the interrupt flag so that if something else happens
442 ; while we faff, the interrupt will be regenerated:
447 mov_lw (1<<WCOL) | (1<<SSPOV)
451 ; 8cy from entry to here, so total of 15cy
452 bt_f_if1 st, st_reading
453 bra s_event_reading ; 18cy to 1st insn of event_reading
455 bt_f_if1 st, st_writing
459 chkvals_start SSPSTAT
460 chkvals_addrrecv 0 ; 23cy to 1st insn of addrrecvread
462 panic morse_SS ; slave, interrupt, controller in bad state
464 ;========================================
468 s_event_idle_addrrecvread
470 goto i2csu_read_begin ; 26cy until 1st insn of read_begin
474 bs_f st, st_awaiting ; (probably)
476 chkvals_start SSPSTAT
477 chkval 0, 0xac, i2csu_read_another ; D,!P, S,R,!BF
478 ; 23cy until 1st insn of i2csu_read_another
480 ; Whatever is happening, we're done reading now !
484 chkvals_start SSPSTAT
485 chkval 0, 0xa8, s_event_reading_datanack ; D,!P, S,!R,!BF
486 ; Or, maybe it was nack and then we were reselected:
487 chkvals_addrrecv 0xa8
493 ; W byte for master any
494 ; State Transmit-Wait Transmit-Busy
498 bt_f_if0 st, st_awaiting
499 bra improper_read_done_data
502 s_event_reading_datanack
505 ;========================================
509 s_event_idle_addrrecvwrite
510 bs_f SSPCON1, 3 ; we'll need the Stop interrupt
512 ; well, this is all fine so far, so do carry on:
515 ; W any byte from master
516 ; i2c controller waiting due to SEN etc continuing with next byte
523 chkvals_start SSPSTAT
524 chkval 0, 0xa9, s_event_writing_datarecv ; D,!P, S,W,BF
526 ; Well, we're done writing now in any case
528 bc_f SSPCON1, 3 ; no Start and Stop interrupts any more
529 call i2csu_write_done
531 ; Who knows what might have happened. We may have
532 ; missed a number of S and P due to delay between
533 ; clearing SSPIF and SSPM3(s&p-intrs) so we can't be
536 ; First, the nice cases:
537 chkvals_start SSPSTAT
542 and_lw 0xc7 ; ?D_A, ?P; ?S
543 xor_lw 0x80 ; SMP, !CKE, !R_W, !UA, !BF
551 s_event_writing_datarecv
552 rcall s_write_slurpbyte
554 bt_f_if1 st, st_subsequent
555 goto i2csu_write_another
556 ; not subsequent (yet):
558 bs_f st, st_subsequent
559 goto i2csu_write_begin
561 ;======================================================================