1 ;######################################################################
2 ; i2clib.inc - I2C LIBRARY - IMPLEMENTATION
4 ; See i2clib.asm for documentation of the interface to this file.
6 include /usr/share/gputils/header/p18f458.inc
8 include ../iwjpictest/insn-aliases.inc
10 include ../iwjpictest/clockvaries.inc
12 include morse+auto.inc
15 ;======================================================================
20 ; m_... routines used by master only
21 ; s_... routines used by slave only
22 ; <any other name> routines used by both
24 ; [ms]_event_... event handler, branched to from interrupt
25 ; handler; conditions are as in the name;
26 ; should `return' at end which will return
27 ; from i2c[ms]_interrupt
29 ; [sm]_event_bad[_...] event handler which panics; called when i2c
30 ; controller did something unexpected
32 ; m_improper_... panics; called when main program
33 ; does something wrong
35 ; [ms]_<anything else> routines or labels of some other kind
37 ; Whenever flow does not pass past the end of some code, we
38 ; have a boundary `;----------', and when flow passes past
39 ; an important label we sometimes mark it specially with `;...',
44 ; bt_f_if0 st, st_something
48 ; m_event_several_including_spong
49 ; bs_f st, st_sponging
50 ; bra metasyntacticing
55 ;============================================================
56 ; COMMON ADMINISTRATIVE ROUTINES and VARIABLES
60 sspstat res 1 ; master only
61 sspcon1 res 1 ; master only
62 sspcon2 res 1 ; master only
63 slave res 1 ; master only
64 slave_next res 1 ; master only
69 ; st is a bitmask, bit set in visible states:
71 st_starting equ 7 ; Writing-Setup?, Reading-Busy?
72 st_addressing equ 6 ; Writing-Setup?, Reading-Busy?
73 st_writing equ 5 ; Writing-*, Stopping(after Reading-Wait:write_start)
74 st_subsequent equ 4 ; Writing?
75 st_reading equ 3 ; Reading-*
76 st_awaiting equ 2 ; Reading-Wait
77 st_acking equ 1 ; Reading-Busy?, Stopping(from read)
78 st_stopping equ 0 ; Stopping
79 ; ...? means not always set in that state
85 ; computes slave address in form suitable for use in i2c controller
86 ; actual i2c slave address is (slave number) + 0b0001000
87 ; W slave number i2c address * 2
93 improper_read_done_data
96 ;======================================================================
105 mov_lw 0x08 ; !SSPEN, Master mode
107 clr_f SSPCON2 ; nothing going
108 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
110 bc_f IPR1, SSPIP ; low priority
117 ; We have an interrupt:
119 i2cm_interrupt_definite
121 mov_ff SSPSTAT, sspstat
122 mov_ff SSPCON1, sspcon1
123 mov_ff SSPCON2, sspcon2
127 mov_lw (1<<WCOL) | (1<<SSPOV)
131 ; No ? Well, then the I2C should be idle now:
133 and_lw ~((1<<ACKSTAT) | (1<<ACKDT)) ; those two are ok if set
137 bt_f_if1 sspstat, R_W
140 bt_f_if1 st, st_stopping
141 bra m_event_done_stopping
143 bt_f_if1 st, st_starting
144 bra m_event_done_starting
147 bt_f_if1 st, st_addressing
148 bra m_event_done_addressing
150 bt_f_if1 st, st_acking
151 bra m_event_done_acking
153 bt_f_if1 st, st_writing
154 bra m_event_done_writing
156 bt_f_if1 st, st_reading
157 bra m_event_done_reading
162 ;========================================
163 ; MASTER - STARTING, ADDRESSING, STOPPING
167 ; st checked for busyness correct
168 ; st_reading/writing one set, one clear unchanged
169 ; st_starting clear set
171 ; slave any slave_number
172 ; expects to return directly to main program (caller)
178 bra_nz m_improper_slave
191 m_event_done_starting
195 bt_f_if1 st, st_reading
196 bs_w 0 ; address bottom bit means read
200 bs_f st, st_addressing
204 m_event_done_addressing
205 bt_f_if1 sspcon2, ACKSTAT
206 bra m_bad_address_ack
209 bc_f st, st_addressing
210 bt_f_if1 st, st_reading
211 bra m_event_done_addressing_read
212 bra m_event_done_addressing_write
216 ; st_stopping clear set
217 ; st_reading/acking/writing any unchanged
218 ; expects to return directly to main program or to end interrupt handler
224 m_event_done_stopping
232 ;========================================
238 ; State Idle/Reading-Wait Writing-Setup
242 bra m_write_start_busy
249 ; Did slave ack our byte ? It had better have done !
250 bt_f_if1 sspcon2, ACKSTAT
253 bs_f st, st_subsequent
256 m_event_done_addressing_write
258 ; st_addressing cleared
259 call i2cmu_write_next_byte
260 bra_z m_event_write_mustfinish
261 ; OK, we have the next byte:
267 m_event_write_mustfinish
268 bt_f_if0 st, st_subsequent
269 bra m_improper_write_finish
274 m_improper_write_finish
277 ;========================================
283 ; State Idle Reading-Busy
286 bra m_read_start_busy
295 bt_f_if1 st, st_awaiting
296 bra m_address_different
301 ; Main program would like to address another slave for reading.
303 tst_f_ifnz slave_next
308 m_event_done_addressing_read
309 m_event_done_acking_readmore
311 ; st_addressing/acking cleared
323 goto i2cmu_read_got_byte
327 ; State Reading-Wait Reading-Busy
328 bt_f_if0 st, st_awaiting
329 bra m_improper_read_another
330 ; OK, we're fine to read another:
334 ; st_reading 1 iff not done unchanged
335 ; st_awaiting still set cleared
336 ; st_acking clear set
337 ; expects to return directly to main program or to end interrupt handler
340 bc_f SSPCON2, ACKDT ; ACKDT=0 means to acknowledge
341 bt_f_if0 st, st_reading
342 bs_f SSPCON2, ACKDT ; don't ack last byte
348 ; State Reading-Wait Stopping
351 bt_f_if0 st, st_awaiting
352 bra improper_read_done_data
361 bt_f_if1 st, st_reading
362 bra m_event_done_acking_readmore
366 ; ok, we want to read another:
369 bt_f_if0 st, st_writing ; because of i2cm_write_start ?
370 bs_f st, st_reading ; no, then we will want to read
372 bra m_start_or_restart
375 m_improper_read_another
378 ;======================================================================
383 ; W slave number undefined
387 mov_lw 0x16 ; !SSPEN, CKP(release), I2C 7-bit slave no-SP-int
389 mov_lw 0x01 ; !GCEN, SEN
391 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
393 bs_f IPR1, SSPIP ; high priority
395 ; Actually engages the I2C controller, which must already have
396 ; been set up (all but SSPEN):
397 ; SSPADD,SSPCON1,SSPCON2 configured correctly unchanged
398 ; SSPSTAT configured correctly unchanged, except:
399 ; SSPSTAT<SSPEN> 0 (disabled) 1 (enabled)
400 ; SSPIE 0 (disabled) 1 (enabled)
401 ; SSPIF configured correctly unchanged
402 ; TRISB<1,0> any configured for I2C
403 ; SSPIP any configured correctly
404 ; GIEL 0 (disabled) 0 (disabled)
405 ; ssp* shadows any all bits set
416 ;========================================
419 ; In general, we figure out our state and then see what kind of events
420 ; we were expecting. Bits we want to check:
421 ; 80 40 20 10 08 04 02 01
422 ; SMP CKE D_A P S R_W UA BF
423 ; set clr data? stop start read? clr full?
424 ; (we don't usually mention SMP, CKE and UA below)
426 ; Labels of the form s_event_* are branches of the interrupt
427 ; handler and are supposed to finish with return.
430 ; Macros: chkvals_start and chkval
432 chkvals_start macro what
436 chkval macro lastval, value, label
437 xor_lw value ^ lastval
444 s_write_slurpbyte macro
445 ; W any byte from master
446 ; i2c controller waiting due to SEN etc continuing with next byte
451 ;----------------------------------------
456 ;----------------------------------------
457 ; branches from the ISR
460 s_event_addrrecvwrite
462 goto i2csu_write_begin
465 s_event_reading_datanack
469 s_event_writing_datarecv
471 goto i2csu_write_data
475 i2cpanic morse_IH ; unknown high-priority interrupt
477 ;----------------------------------------
478 i2cs_interrupt ; 4cy interrupt latency + 3cy until branch to here
481 ; We have an interrupt:
483 mov_lw (1<<WCOL) | (1<<SSPOV)
487 ; Firstly, clear the interrupt flag so that if something else happens
488 ; while we faff, the interrupt will be regenerated:
491 chkvals_start SSPSTAT
492 chkval 0, 0x8c, i2csu_read_begin ;A,!P, S,R,!BF
493 chkval 0x8c,0xac, i2csu_read_another ;D,!P, S,R,!BF
494 chkval 0xac,0x89, s_event_addrrecvwrite ;A,!P, S,W,BF
495 chkval 0x89,0xa9, s_event_writing_datarecv ;D,!P, S,W,BF
496 chkval 0xa9,0xa8, s_event_reading_datanack ;D,!P, S,!R,!BF
500 ;======================================================================
502 include program+externs.fin
505 include variables+vars.fin