1 ;######################################################################
2 ; i2clib.inc - I2C LIBRARY - IMPLEMENTATION
4 ; See i2clib.asm for documentation of the interface to this file.
6 include /usr/share/gputils/header/p18f458.inc
8 include ../iwjpictest/insn-aliases.inc
11 include ../iwjpictest/clockvaries.inc
13 include morse+auto.inc
15 ;======================================================================
20 ; m_... routines used by master only
21 ; s_... routines used by slave only
22 ; <any other name> routines used by both
24 ; [ms]_event_... event handler, branched to from interrupt
25 ; handler; conditions are as in the name;
26 ; should `return' at end which will return
27 ; from i2c[ms]_interrupt
29 ; [sm]_event_bad[_...] event handler which panics; called when i2c
30 ; controller did something unexpected
32 ; m_improper_... panics; called when main program
33 ; does something wrong
35 ; [ms]_<anything else> routines or labels of some other kind
37 ; Whenever flow does not pass past the end of some code, we
38 ; have a boundary `;----------', and when flow passes past
39 ; an important label we sometimes mark it specially with `;...',
44 ; bt_f_if0 st, st_something
48 ; m_event_several_including_spong
49 ; bs_f st, st_sponging
50 ; bra metasyntacticing
55 ;============================================================
56 ; COMMON ADMINISTRATIVE ROUTINES and VARIABLES
62 sspcon2 res 1 ; master only
63 slave res 1 ; master only
64 slave_next res 1 ; master only
69 ; st is a bitmask, bit set in visible states:
71 st_starting equ 7 ; Writing-Setup?,Reading-Busy?
72 st_addressing equ 6 ; Writing-Setup?,Reading-Busy?
73 st_writing equ 5 ; Writing-* [Idle-going-]Receiving
74 st_subsequent equ 4 ; Writing? Receiving
75 st_reading equ 3 ; Reading-* Transmit-*
76 st_awaiting equ 2 ; Reading-Wait Transmit-Wait
77 st_acking equ 1 ; Reading-Busy?,Stopping(from read)
78 st_stopping equ 0 ; Stopping
79 ; ...? means not always set in that state
84 i2cpanic macro morse_addr
85 ; Like panic but turns off the I2C controller
92 ; computes slave address in form suitable for use in i2c controller
93 ; actual i2c slave address is (slave number) + 0b0001000
94 ; W slave number i2c address * 2
100 improper_read_done_data
103 ;======================================================================
112 mov_lw 0x08 ; !SSPEN, Master mode
114 clr_f SSPCON2 ; nothing going
115 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
117 bc_f IPR1, SSPIP ; low priority
124 ; We have an interrupt:
126 i2cm_interrupt_definite
127 mov_ff SSPSTAT, sspstat
128 mov_ff SSPCON1, sspcon1
129 mov_ff SSPCON2, sspcon2
133 mov_lw (1<<WCOL) | (1<<SSPOV)
137 ; No ? Well, then the I2C should be idle now:
139 and_lw ~((1<<ACKSTAT) | (1<<ACKDT)) ; those two are ok if set
143 bt_f_if1 sspstat, R_W
146 bt_f_if1 st, st_stopping
147 bra m_event_done_stopping
149 bt_f_if1 st, st_starting
150 bra m_event_done_starting
153 bt_f_if1 st, st_addressing
154 bra m_event_done_addressing
156 bt_f_if1 st, st_writing
157 bra m_event_done_writing
159 bt_f_if1 st, st_acking
160 bra m_event_done_acking
162 bt_f_if1 st, st_reading
163 bra m_event_done_reading
168 ;========================================
169 ; MASTER - STARTING, ADDRESSING, STOPPING
173 ; st checked for busyness correct
174 ; st_reading/writing set unchanged
175 ; st_starting clear set
177 ; slave any slave_number
178 ; expects to return directly to main program (caller)
180 bra_z m_improper_slave
184 bra_nz m_improper_slave
189 m_event_done_starting
193 bt_f_if1 st, st_reading
194 bs_w 0 ; address bottom bit means read
198 bs_f st, st_addressing
202 m_event_done_addressing
203 bt_f_if1 sspcon2, ACKSTAT
204 bra m_bad_address_ack
207 bc_f st, st_addressing
208 bt_f_if1 st, st_reading
209 bra m_event_done_addressing_read
210 bra m_event_done_addressing_write
214 ; st_stopping clear set
215 ; st_reading/acking/writing any unchanged
216 ; expects to return directly to main program or to end interrupt handler
222 m_event_done_stopping
235 ;========================================
241 ; State Idle Writing-Setup
244 bra m_improper_write_start
251 ; Did slave ack our byte ? It had better have done !
252 bt_f_if1 sspcon2, ACKSTAT
255 bs_f st, st_subsequent
258 m_event_done_addressing_write
260 ; st_addressing cleared
261 call i2cmu_write_next_byte
262 bra_z m_event_write_mustfinish
263 ; OK, we have the next byte:
269 m_event_write_mustfinish
270 bt_f_if0 st, st_subsequent
271 bra m_improper_write_finish
276 m_improper_write_start
280 m_improper_write_finish
283 ;========================================
289 ; State Idle Reading-Busy
292 bra m_read_start_busy
299 bt_f_if1 st, st_awaiting
305 ; Main program would like to address another slave.
307 bra_z m_improper_slave
311 m_event_done_addressing_read
312 m_event_done_acking_readmore
314 ; st_addressing/acking cleared
326 goto i2cmu_read_got_byte
330 ; State Reading-Wait Reading-Busy
331 bt_f_if0 st, st_awaiting
332 bra m_improper_read_another
333 ; OK, we're fine to read another:
337 ; st_reading 1 iff not done unchanged
338 ; st_awaiting still set cleared
339 ; st_acking clear set
340 ; expects to return directly to main program or to end interrupt handler
343 bc_f SSPCON2, ACKDT ; ACKDT=0 means to acknowledge
344 bt_f_if0 st, st_reading
345 bs_f SSPCON2, ACKDT ; don't ack last byte
351 ; State Reading-Wait Stopping
354 bt_f_if0 st, st_awaiting
355 bra improper_read_done_data
364 bt_f_if1 st, st_reading
365 bra m_event_done_acking_readmore
369 ; ok, we want to read another:
374 bra m_start_or_restart
377 m_improper_read_another
380 ;======================================================================
385 ; W slave number undefined
389 mov_lw 0x16 ; !SSPEN, CKP(release), I2C 7-bit slave no-SP-int
391 mov_lw 0x01 ; !GCEN, SEN
393 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
395 bs_f IPR1, SSPIP ; high priority
397 ; Actually engages the I2C controller, which must already have
398 ; been set up (all but SSPEN):
399 ; SSPADD,SSPCON1,SSPCON2 configured correctly unchanged
400 ; SSPSTAT configured correctly unchanged, except:
401 ; SSPSTAT<SSPEN> 0 (disabled) 1 (enabled)
402 ; SSPIE 0 (disabled) 1 (enabled)
403 ; SSPIF configured correctly unchanged
404 ; TRISB<1,0> any configured for I2C
405 ; SSPIP any configured correctly
406 ; GIEL 0 (disabled) 0 (disabled)
407 ; ssp* shadows any all bits set
418 ;========================================
419 ; SLAVE - INTERRUPT HANDLING
421 ; In general, we figure out our state and then see what kind of events
422 ; we were expecting. Bits we want to check:
423 ; 80 60 20 10 08 04 02 01
424 ; SMP CKE D_A P S R_W UA BF
425 ; set clr data? stop start read? clr full?
426 ; (we don't usually mention SMP, CKE and UA below)
428 ; Labels of the form s_event_* are branches of the interrupt
429 ; handler and are supposed to finish with return.
433 chkvals_start macro what
437 chkval macro lastval, value, label
438 xor_lw value ^ lastval
442 chkvals_addrrecv macro lastval
443 chkval lastval, 0x8c, s_event_idle_addrrecvread ; A,!P, S,R,!BF
444 chkval 0x8c, 0x89, s_event_idle_addrrecvwrite ; A,!P, S,W,BF
446 chkvals_addrrecv_lastval equ 0x89
449 i2cs_interrupt ; 4cy interrupt latency + 3cy until branch to here
452 ; We have an interrupt:
454 ; Firstly, clear the interrupt flag so that if something else happens
455 ; while we faff, the interrupt will be regenerated:
460 mov_lw (1<<WCOL) | (1<<SSPOV)
464 ; 8cy from entry to here, so total of 15cy
465 bt_f_if1 st, st_reading
466 bra s_event_reading ; 18cy to 1st insn of event_reading
468 bt_f_if1 st, st_writing
472 chkvals_start SSPSTAT
473 chkvals_addrrecv 0 ; 23cy to 1st insn of addrrecvread
475 i2cpanic morse_SS ; slave, interrupt, controller in bad state
478 i2cpanic morse_IH ; unknown high-priority interrupt
480 ;========================================
484 s_event_idle_addrrecvread
486 goto i2csu_read_begin ; 26cy until 1st insn of read_begin
490 bs_f st, st_awaiting ; (probably)
493 xor_lw 0xac ; D,!P, S,R,!BF
494 bra_nz s_event_reading_not_another
495 goto i2csu_read_another
496 ; 24cy until 1st insn of i2csu_read_another
499 s_event_reading_datanack
503 s_event_reading_not_another
504 ; Whatever is happening, we're done reading now !
508 chkvals_start SSPSTAT
509 chkval 0, 0xa8, s_event_reading_datanack ; D,!P, S,!R,!BF
510 ; Or, maybe it was nack and then we were reselected:
511 chkvals_addrrecv 0xa8
517 ; W byte for master any
518 ; State Transmit-Wait Transmit-Busy
522 bt_f_if0 st, st_awaiting
523 bra improper_read_done_data
528 ;========================================
532 s_event_idle_addrrecvwrite
533 bs_f SSPCON1, 3 ; we'll need the Stop interrupt
535 ; well, this is all fine so far, so do carry on:
538 ; W any byte from master
539 ; i2c controller waiting due to SEN etc continuing with next byte
546 chkvals_start SSPSTAT
547 chkval 0, 0xa9, s_event_writing_datarecv ; D,!P, S,W,BF
549 ; Well, we're done writing now in any case
551 bc_f SSPCON1, 3 ; no Start and Stop interrupts any more
552 call i2csu_write_done
554 ; Who knows what might have happened. We may have
555 ; missed a number of S and P due to delay between
556 ; clearing SSPIF and SSPM3(s&p-intrs) so we can't be
559 ; First, the nice cases:
560 chkvals_start SSPSTAT
565 and_lw 0xc7 ; ?D_A, ?P; ?S
566 xor_lw 0x80 ; SMP, !CKE, !R_W, !UA, !BF
571 s_event_writing_datarecv
572 rcall s_write_slurpbyte
574 bt_f_if1 st, st_subsequent
575 goto i2csu_write_another
577 bs_f st, st_subsequent
578 goto i2csu_write_begin
581 ;======================================================================