1 ;######################################################################
2 ; i2clib.inc - I2C LIBRARY - IMPLEMENTATION
4 ; See i2clib.asm for documentation of the interface to this file.
6 include /usr/share/gputils/header/p18f458.inc
8 include ../iwjpictest/insn-aliases.inc
11 include ../iwjpictest/clockvaries.inc
13 include morse+auto.inc
15 ;======================================================================
20 ; m_... routines used by master only
21 ; s_... routines used by slave only
22 ; <any other name> routines used by both
24 ; [ms]_event_... event handler, branched to from interrupt
25 ; handler; conditions are as in the name;
26 ; should `return' at end which will return
27 ; from i2c[ms]_interrupt
29 ; [sm]_event_bad[_...] event handler which panics; called when i2c
30 ; controller did something unexpected
32 ; m_improper_... panics; called when main program
33 ; does something wrong
35 ; [ms]_<anything else> routines or labels of some other kind
37 ; Whenever flow does not pass past the end of some code, we
38 ; have a boundary `;----------', and when flow passes past
39 ; an important label we sometimes mark it specially with `;...',
44 ; bt_f_if0 st, st_something
48 ; m_event_several_including_spong
49 ; bs_f st, st_sponging
50 ; bra metasyntacticing
55 ;============================================================
56 ; COMMON ADMINISTRATIVE ROUTINES and VARIABLES
62 sspcon2 res 1 ; master only
63 slave res 1 ; master only
64 slave_next res 1 ; master only
69 ; st is a bitmask, bit set in visible states:
71 st_starting equ 7 ; Writing-Setup?,Reading-Busy?
72 st_addressing equ 6 ; Writing-Setup?,Reading-Busy?
73 st_writing equ 5 ; Writing-* [Idle-going-]Receiving
74 st_subsequent equ 4 ; Writing? Receiving
75 st_reading equ 3 ; Reading-* Transmit-*
76 st_awaiting equ 2 ; Reading-Wait Transmit-Wait
77 st_acking equ 1 ; Reading-Busy?,Stopping(from read)
78 st_stopping equ 0 ; Stopping
79 ; ...? means not always set in that state
84 i2cpanic macro morse_addr
85 ; Like panic but turns off the I2C controller
92 ; computes slave address in form suitable for use in i2c controller
93 ; actual i2c slave address is (slave number) + 0b0001000
94 ; W slave number i2c address * 2
100 improper_read_done_data
103 ;======================================================================
112 mov_lw 0x08 ; !SSPEN, Master mode
114 clr_f SSPCON2 ; nothing going
115 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
117 bc_f IPR1, SSPIP ; low priority
124 ; We have an interrupt:
126 mov_ff SSPSTAT, sspstat
127 mov_ff SSPCON1, sspcon1
128 mov_ff SSPCON2, sspcon2
132 mov_lw (1<<WCOL) | (1<<SSPOV)
136 ; No ? Well, then the I2C should be idle now:
138 and_lw ~((1<<ACKSTAT) | (1<<ACKDT)) ; those two are ok if set
142 bt_f_if1 sspstat, R_W
145 bt_f_if1 st, st_stopping
146 bra m_event_done_stopping
148 bt_f_if1 st, st_starting
149 bra m_event_done_starting
152 bt_f_if1 st, st_addressing
153 bra m_event_done_addressing
155 bt_f_if1 st, st_writing
156 bra m_event_done_writing
158 bt_f_if1 st, st_acking
159 bra m_event_done_acking
161 bt_f_if1 st, st_reading
162 bra m_event_done_reading
167 ;========================================
168 ; MASTER - STARTING, ADDRESSING, STOPPING
172 ; st checked for busyness correct
173 ; st_reading/writing set unchanged
174 ; st_starting clear set
176 ; slave any slave_number
177 ; expects to return directly to main program (caller)
179 bra_z m_improper_slave
183 bra_nz m_improper_slave
188 m_event_done_starting
192 bt_f_if1 st, st_reading
193 bs_w 0 ; address bottom bit means read
197 bs_f st, st_addressing
201 m_event_done_addressing
202 bt_f_if1 sspcon2, ACKSTAT
203 bra m_bad_address_ack
206 bc_f st, st_addressing
207 bt_f_if1 st, st_reading
208 bra m_event_done_addressing_read
209 bra m_event_done_addressing_write
213 ; st_stopping clear set
214 ; st_reading/acking/writing any unchanged
215 ; expects to return directly to main program or to end interrupt handler
221 m_event_done_stopping
234 ;========================================
240 ; State Idle Writing-Setup
243 bra m_improper_write_start
250 ; Did slave ack our byte ? It had better have done !
251 bt_f_if1 sspcon2, ACKSTAT
254 bs_f st, st_subsequent
257 m_event_done_addressing_write
259 ; st_addressing cleared
260 call i2cmu_write_next_byte
261 bra_z m_event_write_mustfinish
262 ; OK, we have the next byte:
268 m_event_write_mustfinish
269 bt_f_if0 st, st_subsequent
270 bra m_improper_write_finish
275 m_improper_write_start
279 m_improper_write_finish
282 ;========================================
288 ; State Idle Reading-Busy
291 bra m_read_start_busy
298 bt_f_if1 st, st_awaiting
304 ; Main program would like to address another slave.
306 bra_z m_improper_slave
310 m_event_done_addressing_read
311 m_event_done_acking_readmore
313 ; st_addressing/acking cleared
325 goto i2cmu_read_got_byte
329 ; State Reading-Wait Reading-Busy
330 bt_f_if0 st, st_awaiting
331 bra m_improper_read_another
332 ; OK, we're fine to read another:
336 ; st_reading 1 iff not done unchanged
337 ; st_awaiting still set cleared
338 ; st_acking clear set
339 ; expects to return directly to main program or to end interrupt handler
342 bc_f SSPCON2, ACKDT ; ACKDT=0 means to acknowledge
343 bt_f_if0 st, st_reading
344 bs_f SSPCON2, ACKDT ; don't ack last byte
350 ; State Reading-Wait Stopping
353 bt_f_if0 st, st_awaiting
354 bra improper_read_done_data
363 bt_f_if1 st, st_reading
364 bra m_event_done_acking_readmore
368 ; ok, we want to read another:
373 bra m_start_or_restart
376 m_improper_read_another
379 ;======================================================================
384 ; W slave number undefined
388 mov_lw 0x16 ; !SSPEN, CKP(release), I2C 7-bit slave no-SP-int
390 mov_lw 0x01 ; !GCEN, SEN
392 mov_lw 0x80 ; SMP(noslew), !CKE(!smbus)
394 bs_f IPR1, SSPIP ; high priority
396 ; Actually engages the I2C controller, which must already have
397 ; been set up (all but SSPEN):
398 ; SSPADD,SSPCON1,SSPCON2 configured correctly unchanged
399 ; SSPSTAT configured correctly unchanged, except:
400 ; SSPSTAT<SSPEN> 0 (disabled) 1 (enabled)
401 ; SSPIE 0 (disabled) 1 (enabled)
402 ; SSPIF configured correctly unchanged
403 ; TRISB<1,0> any configured for I2C
404 ; SSPIP any configured correctly
405 ; GIEL 0 (disabled) 0 (disabled)
406 ; ssp* shadows any all bits set
417 ;========================================
418 ; SLAVE - INTERRUPT HANDLING
420 ; In general, we figure out our state and then see what kind of events
421 ; we were expecting. Bits we want to check:
422 ; 80 60 20 10 08 04 02 01
423 ; SMP CKE D_A P S R_W UA BF
424 ; set clr data? stop start read? clr full?
425 ; (we don't usually mention SMP, CKE and UA below)
427 ; Labels of the form s_event_* are branches of the interrupt
428 ; handler and are supposed to finish with retfie_r.
432 chkvals_start macro what
436 chkval macro lastval, value, label
437 xor_lw value ^ lastval
441 chkvals_addrrecv macro lastval
442 chkval lastval, 0x8c, s_event_idle_addrrecvread ; A,!P, S,R,!BF
443 chkval 0x8c, 0x89, s_event_idle_addrrecvwrite ; A,!P, S,W,BF
445 chkvals_addrrecv_lastval equ 0x89
448 i2cs_interrupt ; 4cy interrupt latency + 3cy until branch to here
451 ; We have an interrupt:
453 ; Firstly, clear the interrupt flag so that if something else happens
454 ; while we faff, the interrupt will be regenerated:
459 mov_lw (1<<WCOL) | (1<<SSPOV)
463 ; 8cy from entry to here, so total of 15cy
464 bt_f_if1 st, st_reading
465 bra s_event_reading ; 18cy to 1st insn of event_reading
467 bt_f_if1 st, st_writing
471 chkvals_start SSPSTAT
472 chkvals_addrrecv 0 ; 23cy to 1st insn of addrrecvread
474 i2cpanic morse_SS ; slave, interrupt, controller in bad state
477 i2cpanic morse_IH ; unknown high-priority interrupt
479 ;========================================
483 s_event_idle_addrrecvread
485 call i2csu_read_begin ; 26cy until 1st insn of read_begin
490 bs_f st, st_awaiting ; (probably)
493 xor_lw 0xac ; D,!P, S,R,!BF
494 bra_nz s_event_reading_not_another
495 call i2csu_read_another
496 ; 24cy until 1st insn of i2csu_read_another
497 s_event_reading_datanack
501 s_event_reading_not_another
502 ; Whatever is happening, we're done reading now !
506 chkvals_start SSPSTAT
507 chkval 0, 0xa8, s_event_reading_datanack ; D,!P, S,!R,!BF
508 ; Or, maybe it was nack and then we were reselected:
509 chkvals_addrrecv 0xa8
515 ; W byte for master any
516 ; State Transmit-Wait Transmit-Busy
520 bt_f_if0 st, st_awaiting
521 bra improper_read_done_data
526 ;========================================
530 s_event_idle_addrrecvwrite
531 bs_f SSPCON1, 3 ; we'll need the Stop interrupt
533 ; well, this is all fine so far, so do carry on:
536 ; W any byte from master
537 ; i2c controller waiting due to SEN etc continuing with next byte
544 chkvals_start SSPSTAT
545 chkval 0, 0xa9, s_event_writing_datarecv ; D,!P, S,W,BF
547 ; Well, we're done writing now in any case
549 bc_f SSPCON1, 3 ; no Start and Stop interrupts any more
550 call i2csu_write_done
552 ; Who knows what might have happened. We may have
553 ; missed a number of S and P due to delay between
554 ; clearing SSPIF and SSPM3(s&p-intrs) so we can't be
557 ; First, the nice cases:
558 chkvals_start SSPSTAT
563 and_lw 0xc7 ; ?D_A, ?P; ?S
564 xor_lw 0x80 ; SMP, !CKE, !R_W, !UA, !BF
569 s_event_writing_datarecv
570 rcall s_write_slurpbyte
572 bt_f_if1 st, st_subsequent
573 bra s_event_writing_datarecv_subsequent
575 bs_f st, st_subsequent
576 call i2csu_write_begin
579 s_event_writing_datarecv_subsequent
580 rcall i2csu_write_another
584 ;======================================================================