1 ;======================================================================
3 ; common macros & equs etc.
4 ; generally include this at the top of each file.
6 ;----------------------------------------------------------------------
7 ; COMMON INCLUDES and BOILERPLATE
8 include /usr/share/gputils/header/p18f458.inc
11 include morse+auto.inc
12 include ../iwjpictest/insn-aliases.inc
14 include ../iwjpictest/clockvaries.inc
15 include variables+vars.inc
18 ;----------------------------------------------------------------------
19 ; Common conventions for function register notation:
24 ; STATUS Trashed Trashed
25 ; BSR Not used Not used
27 ; TBLPTR*,TABLAT Low ISR Low ISR
28 ; FSR0 Low ISR Low ISR
29 ; FSR1 Low ISR High ISR (detect[1])
30 ; FSR2 Low ISR High ISR (detect[1])
32 ; Trashed May be trashed by any routine anywhere. Saved
33 ; during every ISR entry/exit.
35 ; Low ISR May be used/traashed by any routine run in low-priority
36 ; interrupt, or any routine run during initialisation.
37 ; May therefore not be used in background loop with
38 ; interrupts enabled. May not be used by high-priority
39 ; ISR (unless explicitly saved).
41 ; High ISR May be used/trashed by any routine run in high-priority
42 ; interrupt, or any routine run during initialisation.
43 ; May therefore not be used elsewhere with interrupts
46 ; Only the routines specially noted as intended to
47 ; be called from the High ISR are safe.
50 ; Register is reserved for use by this subsystem, which
51 ; is allowed to expect the value to be preserved.
52 ; Anything else which uses it must save and restore (and
53 ; may also need to disable interrupts, depending on its
56 ; Not High May be used by any routine not running in high-priority
57 ; interrupt. Not saved by high-priority interrupt
58 ; entry/exit, so any high-priority interrupt routine which
59 ; uses this register must save and restore it.
61 ; A routine which is allowed to trash a register may document that it
62 ; saves that register for the benefit of its callers.
64 ; [1] FSR1 and FSR2 on slave pics are reserved exclusively for the
65 ; I2C response and detection code (detect.asm), after det_slave_init.
67 ; General-purpose hardware allocation:
70 ; Timer 0 nmra Disabled
72 ; Timer 1 1ms tick, int. low 1ms tick, int. low
73 ; CCP1 1ms tick, int. low 1ms tick, int. low
74 ; Timer 3 point fire timer point fire timer
77 ;----------------------------------------------------------------------
78 ; Conventional routine names:
80 ; <periph>_local_do Process a master-to-slave command to activate
81 ; a local peripheral (also called on master to
82 ; activate its own local peripherals)
84 ; <periph>_local_init Initialises RAM tables for local peripheral
85 ; and arranges for pins to be set in appropriate
86 ; quiescent state. Configures pic built-in
89 ; <periph>_local_intr Low ISR service routine.
90 ; Checks for, and clears, any relevant interrupt,
91 ; and returns with `return'.
93 ; <periph>_master_do Called when an appropriate message has been
94 ; received from the host.
96 ;----------------------------------------------------------------------
99 ;----------------------------------------
100 ; For entering and leaving Low ISR, saving and restoring STATUS and W
102 enter_interrupt_low macro
103 mov_ff STATUS, isr_low_save_status
104 mov_wf isr_low_save_w
107 return_interrupt_low macro
108 mov_fw isr_low_save_w
109 mov_ff isr_low_save_status, STATUS
113 ;----------------------------------------
114 ; For disabling all interrupts, to make a critical section:
115 ; (for use from main program and Low ISR only)
121 unmask_int_high macro
125 ;----------------------------------------
126 ; For the fix specified in the silicon errata:
127 ; silicon revision B4 issue 4
129 tblrd_postinc_fixup macro
134 tblrd_postdec_fixup macro
139 ;----------------------------------------
140 ; For setting up TBLPTR according to the picno
142 load_perpic_tblptr macro flash_map_base, perpic_entry_size
143 movlw perpic_entry_size
146 mov_lw flash_map_base & 0xff
150 mov_lw flash_map_base >> 8
154 clr_f TBLPTRU ; TBLPTR* -> our point data
157 ;----------------------------------------------------------------------
160 ; A PINSPEC is a constant 0x<bit><port> where <port> is a b c d e
161 ; and <port> is 0 1 2 3 4 5 6 7. Generally p<picno>_<subsystem>_<pin>
162 ; are equ'd for this.
167 p0_booster_shutdown equ 2b
168 p0_booster_overload equ 1b
169 p0_booster_userfault equ 0b
172 p0_rs232_fcout equ 5c
173 pall_perpicled equ 2d
174 pall_pt0reverse equ 7b
176 p0_booster_dirn equ 0c
177 p0_booster_pwm equ 1c
181 bs_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4
185 bc_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4
189 bs_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
193 bc_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
206 pin_ifh macro pinspec
207 bt_f_if1 PORTA + (PORTB-PORTA)*((pinspec-0xa) & 15), pinspec >> 4
210 pin_ifl macro pinspec
211 bt_f_if0 PORTA + (PORTB-PORTA)*((pinspec-0xa) & 15), pinspec >> 4
214 ;----------------------------------------------------------------------