1 ;======================================================================
3 ; common macros & equs etc.
4 ; generally include this at the top of each file.
6 ;----------------------------------------------------------------------
7 ; COMMON INCLUDES and BOILERPLATE
8 include /usr/share/gputils/header/p18f458.inc
11 include morse+auto.inc
12 include ../iwjpictest/insn-aliases.inc
14 include ../iwjpictest/clockvaries.inc
15 include variables+vars.inc
18 ;----------------------------------------------------------------------
19 ; Common conventions for function register notation:
24 ; STATUS Trashed Trashed
25 ; BSR Not used Not used
27 ; TBLPTR*,TABLAT Low ISR Low ISR
28 ; PROD* Low ISR Low ISR
29 ; FSR0 Low ISR Low ISR
30 ; FSR1 Low ISR High ISR (detect[1])
31 ; FSR2 Low ISR High ISR (detect[1])
33 ; Trashed May be trashed by any routine anywhere. Saved
34 ; during every ISR entry/exit.
36 ; Low ISR May be used/traashed by any routine run in low-priority
37 ; interrupt, or any routine run during initialisation.
38 ; May therefore not be used in background loop with
39 ; interrupts enabled. May not be used by high-priority
40 ; ISR (unless explicitly saved).
42 ; High ISR May be used/trashed by any routine run in high-priority
43 ; interrupt, or any routine run during initialisation.
44 ; May therefore not be used elsewhere with interrupts
47 ; Only the routines specially noted as intended to
48 ; be called from the High ISR are safe.
51 ; Register is reserved for use by this subsystem, which
52 ; is allowed to expect the value to be preserved.
53 ; Anything else which uses it must save and restore (and
54 ; may also need to disable interrupts, depending on its
57 ; Not High May be used by any routine not running in high-priority
58 ; interrupt. Not saved by high-priority interrupt
59 ; entry/exit, so any high-priority interrupt routine which
60 ; uses this register must save and restore it.
62 ; A routine which is allowed to trash a register may document that it
63 ; saves that register for the benefit of its callers.
65 ; [1] FSR1 and FSR2 on slave pics are reserved exclusively for the
66 ; I2C response and detection code (detect.asm), after det_slave_init.
68 ; General-purpose hardware allocation:
71 ; Timer 0 nmra Disabled
73 ; Timer 1 1ms tick, int. low 1ms tick, int. low
74 ; CCP1 1ms tick, int. low 1ms tick, int. low
75 ; Timer 3 point fire timer point fire timer
78 ;----------------------------------------------------------------------
79 ; Conventional routine names:
81 ; <periph>_local_do Process a master-to-slave command to activate
82 ; a local peripheral (also called on master to
83 ; activate its own local peripherals)
85 ; <periph>_local_init Initialises RAM tables for local peripheral
86 ; and arranges for pins to be set in appropriate
87 ; quiescent state. Configures pic built-in
90 ; <periph>_local_intr Low ISR service routine.
91 ; Checks for, and clears, any relevant interrupt,
92 ; and returns with `return'.
94 ; <periph>_master_do Called when an appropriate message has been
95 ; received from the host.
97 ;----------------------------------------------------------------------
100 ;----------------------------------------
101 ; For entering and leaving Low ISR, saving and restoring STATUS and W
103 enter_interrupt_low macro
104 mov_ff STATUS, isr_low_save_status
105 mov_wf isr_low_save_w
108 return_interrupt_low macro
109 mov_fw isr_low_save_w
110 mov_ff isr_low_save_status, STATUS
114 ;----------------------------------------
115 ; For disabling all interrupts, to make a critical section:
116 ; (for use from main program and Low ISR only)
118 ; GIEH modified appropriately
119 ; everything else preserved
125 unmask_int_high macro
129 ;----------------------------------------
130 ; For the fix specified in the silicon errata:
131 ; silicon revision B4 issue 4
134 ; TABLAT any data from flash
135 ; TBLPTR* correct incremented/decremented
136 ; everything else any preserved
138 tblrd_postinc_fixup macro
143 tblrd_postdec_fixup macro
148 ;----------------------------------------
149 ; For setting up TBLPTR according to the picno
151 load_perpic_tblptr macro flash_map_base, perpic_entry_size
155 ; W, STATUS, PROD* any undefined
156 ; everything else any preserved
158 mov_lw perpic_entry_size
161 mov_lw flash_map_base & 0xff
165 mov_lw flash_map_base >> 8
169 clr_f TBLPTRU ; TBLPTR* -> our point data
172 ;----------------------------------------------------------------------
175 ; A PINSPEC is a constant 0x<bit><port> where <port> is a b c d e
176 ; and <port> is 0 1 2 3 4 5 6 7. Generally p<picno>_<subsystem>_<pin>
177 ; are equ'd for this.
182 p0_booster_shutdown equ 2b
183 p0_booster_overload equ 1b
184 p0_booster_userfault equ 0b
187 p0_rs232_fcout equ 5c
188 pall_perpicled equ 2d
189 pall_pt0reverse equ 7b
191 p0_booster_dirn equ 0c
192 p0_booster_pwm equ 1c
196 ; LAT* may be subject to read-modify-write, see below
197 ; TRIS* may be subject to read-modify-write, see below
198 ; PORT* may be read, see below
199 ; everything else untouched
201 ; LAT*<bit> TRIS*<bit> PORT*
202 ; pin_z untouched set untouched
203 ; pin_h set cleared untouched
204 ; pin_l cleared cleared untouched
205 ; pin_nz untouched cleared untouched
206 ; pin_vh set untouched untouched
207 ; pin_vl cleared untouched untouched
208 ; pin_ifh untouched untouched read
209 ; pin_ifl untouched untouched read
212 bs_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4
216 bc_f TRISA + (TRISB-TRISA)*((pinspec-0xa) & 15), pinspec >> 4
220 bs_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
224 bc_f LATA + (LATB-LATA)*((pinspec-0xa) & 15), pinspec >> 4
237 pin_ifh macro pinspec
238 bt_f_if1 PORTA + (PORTB-PORTA)*((pinspec-0xa) & 15), pinspec >> 4
241 pin_ifl macro pinspec
242 bt_f_if0 PORTA + (PORTB-PORTA)*((pinspec-0xa) & 15), pinspec >> 4
245 ;----------------------------------------------------------------------