From ad76127c59f4085955320888ba2bcee0ca0cfff1 Mon Sep 17 00:00:00 2001
From: Ian Jackson <ijackson@chiark.greenend.org.uk>
Date: Mon, 16 Oct 2023 23:58:26 +0100
Subject: [PATCH] digispark-with-cable: wip

Signed-off-by: Ian Jackson <ijackson@chiark.greenend.org.uk>
---
 digispark-with-cable.scad | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/digispark-with-cable.scad b/digispark-with-cable.scad
index 279df34..5497431 100644
--- a/digispark-with-cable.scad
+++ b/digispark-with-cable.scad
@@ -14,19 +14,20 @@ side_wall_th = 1.5;
 
 board_l = 13.56 + 0.2;
 board_w = 19.14 + 0.2;
+board_th = 1.92 + 0.1;
 
-module TopSmallWallsPlan() {
+module BothSides(){
   for (m=[0,1]) {
     mirror([m,0]) {
-      rectfromto([ -usb_w/2,              -0.01        ],
-		 [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
+      children();
     }
   }
 }
-module BothSides(){
+module TopSmallWallsPlan() {
   for (m=[0,1]) {
     mirror([m,0]) {
-      children();
+      rectfromto([ -usb_w/2,              -0.01        ],
+		 [ -usb_w/2 + usb_wall_w, usb_tongue_d ]);
     }
   }
 }
@@ -39,7 +40,10 @@ module TopCeilPlan() {
   }
 }
 module TopMainWallsPlan() {
-  
+  BothSides(){
+    rectfromto([ -board_w/2 - side_wall_th, 0            ],
+	       [ -board_w/2,                -board_l     ]);
+  }
 }
 
 module Top(){
@@ -47,6 +51,8 @@ module Top(){
     TopSmallWallsPlan();
   linextr(usb_wall_h - usb_ceil_th, usb_wall_h)
     TopCeilPlan();
+  linextr(-board_th, usb_wall_h)
+    TopMainWallsPlan();
 }
 
 Top();
-- 
2.30.2