Make the project planner always auto-place.

[cura.git] / Cura / avr_isp / stk500v2.py

diff --git a/Cura/avr_isp/stk500v2.py b/Cura/avr_isp/stk500v2.py
index f22f50f9fbc9c1fa948fd557dcd68862e04c8261..a66b341db2212d80ad1787285d4468bd64b033f7 100644 (file)
--- a/Cura/avr_isp/stk500v2.py
+++ b/Cura/avr_isp/stk500v2.py
@@ -10,8 +10,9 @@ class Stk500v2(ispBase.IspBase):
                self.serial = None\r
                self.seq = 1\r
                self.lastAddr = -1\r
+               self.progressCallback = None\r
        \r
-       def connect(self, port = 'COM31', speed = 115200):\r
+       def connect(self, port = 'COM17', speed = 115200):\r
                if self.serial != None:\r
                        self.close()\r
                try:\r
@@ -146,7 +147,7 @@ class Stk500v2(ispBase.IspBase):
 def main():\r
        programmer = Stk500v2()\r
        programmer.connect()\r
-       programmer.programChip(intelHex.readHex("cfg_4f55234def059.hex"))\r
+       programmer.programChip(intelHex.readHex(sys.argv[1]))\r
        sys.exit(1)\r
 \r
 if __name__ == '__main__':\r