1 /* Copyright (C) 1997, 1998, 1999, 2004, 2006,2008 Free Software Foundation, Inc.
2 This file is part of the GNU C Library.
4 The GNU C Library is free software; you can redistribute it and/or
5 modify it under the terms of the GNU Lesser General Public
6 License as published by the Free Software Foundation; either
7 version 2.1 of the License, or (at your option) any later version.
9 The GNU C Library is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 Lesser General Public License for more details.
14 You should have received a copy of the GNU Lesser General Public
15 License along with the GNU C Library; if not, write to the Free
16 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
23 #if defined __NO_FPRS__ && !defined _SOFT_FLOAT /* E500 */
25 /* Define bits representing the exception. We use the bit positions of
26 the appropriate bits in the SPEFSCR... */
29 FE_INEXACT = 1 << (63 - 42),
30 #define FE_INEXACT FE_INEXACT
31 FE_INVALID = 1 << (63 - 43),
32 #define FE_INVALID FE_INVALID
33 FE_DIVBYZERO = 1 << (63 - 44),
34 #define FE_DIVBYZERO FE_DIVBYZERO
35 FE_UNDERFLOW = 1 << (63 - 45),
36 #define FE_UNDERFLOW FE_UNDERFLOW
37 FE_OVERFLOW = 1 << (63 - 46)
38 #define FE_OVERFLOW FE_OVERFLOW
41 #define FE_ALL_EXCEPT \
42 (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
44 /* The E500 support all of the four defined rounding modes. We use
45 the bit pattern in the SPEFSCR as the values for the appropriate
50 #define FE_TONEAREST FE_TONEAREST
52 #define FE_TOWARDZERO FE_TOWARDZERO
54 #define FE_UPWARD FE_UPWARD
56 #define FE_DOWNWARD FE_DOWNWARD
59 /* Type representing exception flags. */
60 typedef unsigned int fexcept_t;
62 typedef double fenv_t;
64 /* If the default argument is used we use this value. */
65 extern const fenv_t __fe_dfl_env;
66 #define FE_DFL_ENV (&__fe_dfl_env)
69 /* Floating-point environment where all exceptions are enabled. Note that
70 this is not sufficient to give you SIGFPE. */
71 extern const fenv_t __fe_enabled_env;
72 # define FE_ENABLED_ENV (&__fe_enabled_env)
74 /* Floating-point environment with all exceptions enabled. Note that
75 just evaluating this value will set the processor into 'FPU
76 exceptions imprecise recoverable' mode, which may cause a significant
77 performance penalty (but have no other visible effect). */
78 extern const fenv_t *__fe_nomask_env (void);
79 # define FE_NOMASK_ENV (__fe_nomask_env ())
82 #else /* PowerPC 6xx floating-point. */
84 /* Define bits representing the exception. We use the bit positions of
85 the appropriate bits in the FPSCR... */
88 FE_INEXACT = 1 << (31 - 6),
89 #define FE_INEXACT FE_INEXACT
90 FE_DIVBYZERO = 1 << (31 - 5),
91 #define FE_DIVBYZERO FE_DIVBYZERO
92 FE_UNDERFLOW = 1 << (31 - 4),
93 #define FE_UNDERFLOW FE_UNDERFLOW
94 FE_OVERFLOW = 1 << (31 - 3),
95 #define FE_OVERFLOW FE_OVERFLOW
97 /* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
98 actually corresponds to bits 7 through 12 and 21 through 23
99 in the FPSCR, but we can't use that because the current draft
100 says that it must be a power of 2. Instead we use bit 2 which
101 is the summary bit for all the FE_INVALID exceptions, which
102 kind of makes sense. */
103 FE_INVALID = 1 << (31 - 2),
104 #define FE_INVALID FE_INVALID
107 /* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
108 input to a routine is equivalent to setting all of these bits;
109 FE_INVALID will be set on output from a routine iff one of
110 these bits is set. Note, though, that you can't disable or
111 enable these exceptions individually. */
113 /* Operation with SNaN. */
114 FE_INVALID_SNAN = 1 << (31 - 7),
115 # define FE_INVALID_SNAN FE_INVALID_SNAN
118 FE_INVALID_ISI = 1 << (31 - 8),
119 # define FE_INVALID_ISI FE_INVALID_ISI
122 FE_INVALID_IDI = 1 << (31 - 9),
123 # define FE_INVALID_IDI FE_INVALID_IDI
126 FE_INVALID_ZDZ = 1 << (31 - 10),
127 # define FE_INVALID_ZDZ FE_INVALID_ZDZ
130 FE_INVALID_IMZ = 1 << (31 - 11),
131 # define FE_INVALID_IMZ FE_INVALID_IMZ
133 /* Comparison with NaN or SNaN. */
134 FE_INVALID_COMPARE = 1 << (31 - 12),
135 # define FE_INVALID_COMPARE FE_INVALID_COMPARE
137 /* Invalid operation flag for software (not set by hardware). */
138 /* Note that some chips don't have this implemented, presumably
139 because no-one expected anyone to write software for them %-). */
140 FE_INVALID_SOFTWARE = 1 << (31 - 21),
141 # define FE_INVALID_SOFTWARE FE_INVALID_SOFTWARE
143 /* Square root of negative number (including -Inf). */
144 /* Note that some chips don't have this implemented. */
145 FE_INVALID_SQRT = 1 << (31 - 22),
146 # define FE_INVALID_SQRT FE_INVALID_SQRT
148 /* Conversion-to-integer of a NaN or a number too large or too small. */
149 FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23)
150 # define FE_INVALID_INTEGER_CONVERSION FE_INVALID_INTEGER_CONVERSION
152 # define FE_ALL_INVALID \
153 (FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
154 | FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \
155 | FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION)
159 #define FE_ALL_EXCEPT \
160 (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
162 /* PowerPC chips support all of the four defined rounding modes. We
163 use the bit pattern in the FPSCR as the values for the
164 appropriate macros. */
168 #define FE_TONEAREST FE_TONEAREST
170 #define FE_TOWARDZERO FE_TOWARDZERO
172 #define FE_UPWARD FE_UPWARD
174 #define FE_DOWNWARD FE_DOWNWARD
177 /* Type representing exception flags. */
178 typedef unsigned int fexcept_t;
180 /* Type representing floating-point environment. We leave it as 'double'
181 for efficiency reasons (rather than writing it to a 32-bit integer). */
182 typedef double fenv_t;
184 /* If the default argument is used we use this value. */
185 extern const fenv_t __fe_dfl_env;
186 #define FE_DFL_ENV (&__fe_dfl_env)
189 /* Floating-point environment where all exceptions are enabled. Note that
190 this is not sufficient to give you SIGFPE. */
191 extern const fenv_t __fe_enabled_env;
192 # define FE_ENABLED_ENV (&__fe_enabled_env)
194 /* Floating-point environment with (processor-dependent) non-IEEE floating
196 extern const fenv_t __fe_nonieee_env;
197 # define FE_NONIEEE_ENV (&__fe_nonieee_env)
201 /* Floating-point environment with all exceptions enabled. Note that
202 just evaluating this value does not change the processor exception mode.
203 Passing this mask to fesetenv will result in a prctl syscall to change
204 the MSR FE0/FE1 bits to "Precise Mode". On some processors this will
205 result in slower floating point execution. This will last until an
206 fenv or exception mask is installed that disables all FP exceptions. */
207 extern const fenv_t *__fe_nomask_env (void);
208 # define FE_NOMASK_ENV FE_ENABLED_ENV
210 /* Floating-point environment with all exceptions disabled. Note that
211 just evaluating this value does not change the processor exception mode.
212 Passing this mask to fesetenv will result in a prctl syscall to change
213 the MSR FE0/FE1 bits to "Ignore Exceptions Mode". On most processors
214 this allows the fastest possible floating point execution.*/
215 extern const fenv_t *__fe_mask_env (void);
216 # define FE_MASK_ENV FE_DFL_ENV