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eglibc (2.11.3-4+deb6u3) squeeze-lts; urgency=medium
[eglibc.git] / nptl / sysdeps / unix / sysv / linux / sh / sh4 / lowlevellock.h
1 /*  4 instruction cycles not accessing cache and TLB are needed after
2     trapa instruction to avoid an SH-4 silicon bug.  */
3 #define NEED_SYSCALL_INST_PAD
4 #include_next <lowlevellock.h>
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